ICS9LPRS525AGILF IDT, Integrated Device Technology Inc, ICS9LPRS525AGILF Datasheet - Page 14

• Manufacturer Part Number: ICS9LPRS525AGILF
• Description: IC CK505 VREG/RES 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of ICS9LPRS525AGILF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1932

IDT
Byte 0 FS Readback and PLL Selection Register
Byte 1 DOT96 Select and PLL3 Quick Config Register
Byte 2 Output Enable Register
Byte 3 Output Enable Register
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ICS9LPRS525
PC MAIN CLOCK
TM
PC MAIN CLOCK
13/14
Pin
Pin
Pin
Pin
-
-
-
-
-
-
-
-
PLL1_SSC_SEL
PLL3_SSC_SEL
SRC_Main_SEL
SRC8/ITP_OE
PD_Restore
SATA_SEL
SRC0_SEL
PCIF5_OE
PLL3_CF3
PLL3_CF2
PLL3_CF1
PLL3_CF0
SRC7_OE
SRC6_OE
SRC5_OE
SRC4_OE
iAMT_EN
Reserved
PCI_SEL
PCI4_OE
PCI3_OE
PCI2_OE
PCI1_OE
PCI0_OE
Reserved
Reserved
Reserved
REF_OE
USB_OE
Name
Name
Name
Name
FSLC
FSLB
FSLA
Set via SMBus or dynamically by CK505 if detects
0 = clear all SMBus configurations as if cold power-
1 = on Power Down de-assert return to last known
This bit is ignored and treated at '1' if device is in
Output enable for REF, if disabled output is tri-
CPU Freq. Sel. Bit (Least Significant)
CPU Freq. Sel. Bit (Most Significant)
Select 0.5% down or center SSC
Select 0.5% down or center SSC
on and go to latches open state
Output enable for SRC8 or ITP
Select source for SATA clock
Select source for SRC Main
PLL3 Quick Config Bit 3
PLL3 Quick Config Bit 2
PLL3 Quick Config Bit 1
PLL3 Quick Config Bit 0
Output enable for SRC7
Output enable for SRC6
Output enable for SRC5
Output enable for SRC4
Select SRC0 or DOT96
Output enable for PCI5
Output enable for PCI4
Output enable for PCI3
Output enable for PCI2
Output enable for PCI1
Output enable for PCI0
Output enable for USB
CPU Freq. Sel. Bit
Description
dynamic M1
iAMT mode.
Description
Description
Description
Reserved
Reserved
Reserved
Reserved
PCI_SEL
stated
state
14
Type
Type
Type
Type
RW
RW
RW
RW SRC Main = PLL1 SRC Main = PLL3 Latch
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
See Table 1 : CPU Frequency Select
Configuration Not
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
PCI from PLL1
Only applies if Byte 0, bit 2 = 0.
Legacy Mode
Down spread
Down spread
SRC_Main
SATA =
Saved
See Table 2: PLL3 Quick
SRC0
0
0
0
0
-
-
-
Configuration
Table
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
iAMT Enabled
SATA = PLL2
Center spread
Center spread
Configuration
SRC_MAIN
PCI from
DOT96
Saved
1
1
1
1
-
-
-
1484C—04/20/10
Default
Default
Default
Default
Latch
Latch
Latch
Latch
1
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1