ICS9LPRS525AGILF IDT, Integrated Device Technology Inc, ICS9LPRS525AGILF Datasheet - Page 16

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ICS9LPRS525AGILF

Manufacturer Part Number
ICS9LPRS525AGILF
Description
IC CK505 VREG/RES 56TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Generatorr
Datasheet

Specifications of ICS9LPRS525AGILF

Input
Crystal
Output
Clock
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Frequency-max
400MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1932

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS9LPRS525AGILF
Manufacturer:
IDT
Quantity:
92
IDT
NOTE: A value of '00' for Bit(3:2) in Byte 11 is reserved and not a valid configuration.
Byte 8 Device ID and Output Enable Register
Byte 9 Output Control Register
Byte 10 Stop Enable Register
Byte 11 iAMT Enable Register
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ICS9LPRS525
PC MAIN CLOCK
TM
PC MAIN CLOCK
Pin
Pin
Pin
Pin
SRC5_EN Readback
CPU 1 Stop Enable
CPU 0 Stop Enable
CPU 2 Stop Enable
Test Mode Select
PCIF5 STOP EN
Test Mode Entry
CPU2_AMT_EN
CPU1_AMT_EN
TME_Readback
REF Strength
PCI-E_GEN2
PCI3_CFG1
PCI3_CFG0
Device_ID3
Device_ID2
Device_ID1
Device_ID0
IO_VOUT2
IO_VOUT1
IO_VOUT0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SE1_OE
SE2_OE
Name
Name
Name
Name
Determines if CPU1 runs in M1 mode. See Note.
differentiating between CK505 package options,
IO Output Voltage Select (Least Significant Bit)
IO Output Voltage Select (Most Significant Bit)
Allows test select, ignores REF/FSC/TestSel
Enables control of CPU 0 with CPU_STOP#
Enables control of CPU 0 with CPU_STOP#
Enables control of CPU1 with CPU_STOP#
Truested Mode Enable (TME) strap status
Table of Device identifier codes, used for
Allows control of PCIF5 with assertion of
Determines if CPU2 runs in M1 mode.
Determines if PCI-E Gen2 compliant
Allows entry into test mode, ignores
Only valid if ITP_EN=1. See Note.
Sets the REF output drive strength
See PCI3 Configuration Table 28
Readback of SRC5 enable latch
IO Output Voltage Select
Output enable for SE1
Output enable for SE2
FSB/TestMode
Description
Description
PCI_STOP#
Description
Description
Reserved
Reserved
Reserved
Reserved
Reserved
etc.
16
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
R
Normal operation
normal operation
CPU/PCI Stop
Does not Run
Does not Run
Free Running
Free Running
Free Running
Outputs HI-Z
Free running
1X (2Loads)
See PCI3 Configuration Table
See Table 3: V_IO Selection
non-Gen2
Disabled
Disabled
Enabled
0
0
0
0
-
-
-
-
-
-
-
-
-
(Default is 0.8V)
56-pin device
Outputs = REF/N
no overclocking
SRC5 Enabled
2X (3 Loads)
PCI_STOP#
PCI-E Gen2
Test mode
Stops with
Stoppable
Stoppable
Compliant
Stoppable
assertion
Enabled
Enabled
Runs
Runs
1
1
1
1
-
-
-
-
-
-
-
-
-
1484C—04/20/10
Default
Default
Default
Default
Latch
Latch
Latch
Latch
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
1
0
1
0
1
1
1

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