PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 454

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Read program control and status word
SYNTAX
FUNCTION
DESCRIPTION
rdest. The layout of PCSW is shown below.
occur during program execution. Thus,
what events have occurred; this operation can also be used to save state before idling a task in a multi-tasking
environment.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
exception trap enable
PCSW = 0x80110642
r20 = 0, PCSW = 0x80000000
r21 = 1, PCSW = 0x80000000
Misaligned store exception
PCSW<31:16>
The
Fields in the PCSW have two chief purposes: to control aspects of processor operation and to record events that
The
[ IF rguard ] readpcsw → rdest
if rguard then {
}
PCSW<15:0>
Write back error trap enable
rdest ← PCSW
Misaligned store
readpcsw
readpcsw
Reserved exception
Write back error
Initial Values
MSE
MSE
TRP
15
31
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
writes the current value of the PCSW (Program Control and Status Word) processor register to
Interrupt enable (1 ⇒ allow interrupts)
WBE RSE
WBE
TRP
14
30
Count stalls (1 ⇒ Yes)
Reserved exception
trap enable
TRP
RSE
29
13
readpcsw → r100
IF r20 readpcsw → r101
IF r21 readpcsw → r102
U N D E F
12
28
U N D E F
readpcsw
CS
11
27
Operation
TFE
IEN
10
26
Trap on first exit
can be used to determine current processor operating modes and
BSX IEEE MODE OFZ
25
9
U N D E F I N E D
Byte sex (1 ⇒ little endian)
PRELIMINARY SPECIFICATION
8
IEEE rounding mode
0 ⇒ to nearest, 1 ⇒ to zero, 2 ⇒ to positive, 3 ⇒ to negative
23
7
r100
enabled, IEN=1 - interrupts enabled, BSX=1 - little
endian mode of operation, OFZ=1 - a denormalized
result was produced somewhere, INX=1 - an inexact
result was produced somewhere)
no change, since guard is false
r102
PNX1300/01/02/11 DSPCPU Operations
TRP
OFZ
22
6
← 0x80110642 (trap on MSE, INV and DBZ
← 0x80000000 (trap on MSE enabled)
TRP
IFZ
IFZ
21
5
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
FP exception trap-enable bits
TRP
INV
INV
20
4
FP exceptions
Result
OVF
TRP
OVF
ATTRIBUTES
19
writepcsw
3
SEE ALSO
readpcsw
UNF
TRP
UNF
18
2
TRP
INX
INX
17
1
fcomp
158
No
—
0
1
3
DBZ
TRP
DBZ
A-156
16
0