PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 257

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Table 17-2 Effect of SSI_CTL.IO1 on SSI_IO1
Table 17-3 Effect of SSI_CTL.IO2 on SSI_IO2
17.3.2
The internal frame synchronization logic is illustrated in
Figure
(TxFSX) is being generated from the transmit or receive
clock selected by SSI_CTL.IO1. The Clock is divided by
the word length (16) and a Frame Rate Divider which is
controlled by the FSS[3:0] bits in the SSI_CTL register.
FMS determines the Frame Mode operation, whether the
frame sync pulse is word-length or bit-length. The trans-
mit
SSI_CTL.IO2, as shown in
Figure 17-3. Frame synchronization generation block diagram
SSI_RxCLK
IO1[0:1]
IO2[0:1]
SSI_IO1
00
01
10
11
00
01
10
11
framing
17-3. An internal Frame Synchronization signal
Frame Synchronization
general purpose output with positive logic
polarity, reflecting the value in
SSI_CTL.WIO1
general purpose input, with optional change
detector function. The input state can be
read from SSI_CSR.RIO1. The change
detector is clocked by the highway bus. The
change detector may optionally generate an
interrupt, under the control of CDE bit of
SSI_CTL.
Transmit clock (TxCLK) input
tri-state, input signal value ignored
General purpose output with positive logic
polarity, reflecting the value in
SSI_CTL.WIO2
General purpose input. The input state can
be read in from SSI_CSR.RIO2. No change
detector is provided for this pin.
Internal transmit framing signal (TxFSX) out-
put.
Transmit framing signal (TxFSX) input.
signal
IO1[1:0]=10
IO1[1:0]=10
Function of SSI_IO1
Function of SSI_IO2
is
Table
MUX
selected
2:1
17-4.
TxCLK
depending
Word Length
Divider
on
Table 17-4. Effect of SSI_CTL.IO2 on transmit
framing signal
17.3.3
The transmitter control block diagram is illustrated in
Figure
two sources, i.e. SSI_IO1 or SSI_RxCLK by program-
ming IO1[1:0] bits in the SSI_CTL register (see
Figure
falling edge of the clock, which can be configured with
SSI_CTL.TCP.
The transmitter has a 30-entry deep, 16-bit transmit
buffer that buffers the data between the 32-bit
SSI_TXDR register and the 16-bit transmit shift register
(TxSR).
The TxSR is a 16-bit transmit shift register. It can be con-
figured to shift out MSB or LSB first with SSI_CTL.TSD.
A detailed description of the configuration of the transmit-
ter can be found in the SSI_CTL and SSI_CSR register
description
SSI_TxDR is a 32-bit MMIO transmit register.
17.3.4
The receiver control block diagram is illustrated in
Figure
and data signal are always taken from the external pins.
The receiver has a 32-entry deep, 16-bit receive buffer
that buffers the data between the 16-bit receive shift reg-
ister (RxSR) and the 32-bit SSI_RXDATA register.
The input pin SSI_RxDATA provides serial shift in data
to the RxSR. The RxSR is a 16-bit receive shift register.
RxSR can be configured to shift in from MSB or LSB first
using SSI_CTL.RSD. A transfer takes place on either the
rising or falling edge of the receiver clock, which can be
configured with the SSI_CTL.RCP.
PRELIMINARY SPECIFICATION
Frame Rate
IO2[0:1]
Divider
FSS[3:0]
00
01
10
11
17-4. The transmitter clock can be selected from
17-2). A transfer takes place on either the rising or
17-5. The receiver clock, frame synchronization
SSI Transmit
SSI Receive
taken from RxFSX
taken from RxFSX
internally generated
taken from SSI_IO2 pin
(17.10.1
Source of transmit framing signal
Frame Sync
and 17.10.2)
Synchronous Serial Interface
Mode
FMS
internal TxFSX
17-3