PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 28

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
1.4
In the table below, a pin name ending in a ‘#’ designates an active-low signal (the active state of the signal is a low
voltage level). All other signals have active-high polarity.
1-2
TRI_CLKIN
VDDQ
VSSQ
TRI_RESET#
BOOT_CLK
TESTMODE
SCANCPU
RESERVED1
RESERVED2
VREF_PCI
VREF_PERIPH
TRI_USERIRQ
TRI_TIMER_CLK
Pin Name
SIGNAL PIN LIST
BGA
Ball
G19
D20
D19
C18
G20
H19
L20
K20
L19
T20
P19
E19
F2
PRELIMINARY SPECIFICATION
NORM3
NORM3
NORM3
NORM3
NORM3
WEAK5
WEAK5
WEAK5
STRG5
Type
Pad
N/A
N/A
N/A
N/A
Mode
PWR
PWR
PWR
GND
I/O
I/O
IN
IN
IN
IN
IN
IN
IN
Main input clock. The SDRAM clock outputs (MM_CLK0 and MM_CLK1) can be set to
2x or 3x this frequency. The on-chip DSPCPU clock (DSPCPU_CLK) can be set to 1x,
5/4, 4/3, 3/2 or 2x the SDRAM clock frequency. Maximum recommended ppm level is
+/- 100 ppm or lower to improve jitter on generated clocks. Duty cycle should not
exceed 30/70% asymmetry.
The operating limits of the internal PLLs are:
• 27 MHz < Output of the SDRAM PLL < 200 MHz
• 33 MHz < Output of the CPU PLL < 266 MHz
These are not the speed grades of the chips, just the PLL limits.
Quiet VDD for the PLL subsystem. This pin should be supplied from VDD through a
low-Q series inductor. It should be bypassed for AC to VSSQ, using a dual capacitor
bypass (hi and low frequency AC bypass).
Quiet VSS for the PLL subsystem. Should be AC bypassed to VDDQ, but should
otherwise be left DC floating. It is connected on-chip to VSS. No external coil or
other connection to board ground is needed, such connection would create a
ground loop.
PNX1300/01/02/11 RESET input. This pin can be tied to the PCI RST# signal in PCI
bus systems. Upon releasing RESET, PNX1300/01/02/11 initiates its boot protocol.
Used for testing purposes. Must be connected to TRI_CLKIN for normal operation.
Used for testing purposes. Must be connected to VSS for normal operation.
Used for testing purposes. Must be connected to VSS for normal operation.
Reserved pin. Has to be left unconnected for normal operation.
Reserved pin. Has to be left unconnected for normal operation.
VREF_PCI determines the mode of operation of the PCI pins listed in
VREF_PCI must be connected to 5V for use in a 5-V PCI signaling environment or to
VSS (0 V) for use in 3.3-V PCI signaling environment. The supply to this pin should be
AC bypassed and provide 40 mA of DC sink or source capability. Note that this pin
can not be directly connected to the PCI ‘I/O designated power pins’ in a dual
voltage PCI plug-in card. Board level conversion circuitry is required.
VREF_PERIPH determines the mode of operation of the I/O pins listed in
VREF_PERIPH should be connected to 5V if any of the listed I/O pins provided should
be 5-V input voltage capable. VREF_PERIPH should be connected to VSS (0-V) if all
listed I/O pins are 3.3-V only inputs. The supply to this pin should be AC bypassed and
provide 40 mA of DC sink or source capability.
General purpose level/edge interrupt input. Vectored interrupt source number 4.
External general purpose clock source for timers. Max. 40 MHz.
Miscellaneous System Interface
Main Clock Interface
Description
Philips Semiconductors
Section
Section
1.6.
1.6.