PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 263

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
17.10.1 SSI Control Register (SSI_CTL)
SSI_CTL is a 32-bit read/write control register used to direct the operation of the SSI. The value of this register after a
hardware reset is 0x00F00000.
Table 17-5. SSI control register (SSI_CTL) fields.
TXR
RXR
TXE
RXE
TCP
RCP
TSD
RSD
IO1
IO2
WIO1
WIO2
TIE
RIE
FSS
Field
Transmitter Software Reset (Bit 31). Setting TXR performs the same functions as a hardware reset. Resets all
transmitter functions. A transmission in progress is interrupted and the data remaining in the TxSR is lost. The
TxFIFO pointers are reset and the data contained will not be transmitted, but the data in the SSI_TxDR and/or
TxFIFO are not explicitly deleted. The transmitter status and interrupts are all cleared. This is an action bit. This bit
always reads ‘0’. Writing a ‘1’ in combination with writing a ‘1‘ in the RXR field will initiate a reset for the SSI module.
Note: this bit is always set together with RXR because a separate transmitter or receiver reset is not implemented.
Receiver Software Reset (Bit 30). Setting RXR performs the same functions as a hardware reset. Resets all
receiver functions. A reception in progress is interrupted and the data collected in the RxSR is lost. The RxFIFO
pointers are reset, and the SSI will not generate an interrupt to DSPCPU to retrieve data in the SSI_RxDR and/or
RxFIFO. The data in the SSI_RxDR and/or RxFIFO is not explicitly deleted. The receiver status and interrupts are
all cleared.This is an action bit.This bit always reads ‘0’. Writing a ‘1’ in combination with writing a ‘1‘ in the TXR field
will initiate a reset for the SSI module. Note: this bit is always set together with TXR, because a separate transmitter
or receiver reset is not implemented.
Transmitter Enable (Bit 29). TXE enables the operation of the transmit shift register state machine. When TXE is set
and a frame sync is detected, the transmit state machine of the SSI is begins transmission of the frame. When TXE
is cleared, the transmitter will be disabled after completing transmission of data currently in the TxSR. The serial out-
put (SSI_TxDATA) is three-stated, and any data present in SSI_TxDR and/or TxFIFO will not be transmitted (i.e.,
data can be written to SSI_TxDR with TXE cleared; TDE can be cleared, but data will not be transferred to the TxSR).
Status fields updated by the Transmit state machine are not updated or reset when an active transmitter is disabled.
Receive Enable (Bit 28). When RXE is set, the receive state machine of the SSI is enabled. When this bit is cleared,
the receiver will be disabled by inhibiting data transfer into SSI_RxDR and/or RxFIFO. If data is being received while
this bit is cleared, the remainder of that 16-bit word will be shifted in and transferred to the SSI RxFIFO and/or
SSI_RxDR.
Status fields updated by the Receive state machine are not updated or reset when an active receiver is disabled.
Transmit Clock Polarity (Bit 27). The TCP bit value should only be changed when the transmitter is disabled. TCP
controls on which edge of TxCLK data is output. TCP=0 causes data to be output at rising edge of TxCLK, TCP=1
causes data to be output at falling edge of TxCLK.
Receive Clock Polarity (Bit 26). RCP controls which edge of RxCLK samples data. The data is sampled at rising edge
when RCP = ‘1’ or falling edge when RCP = ‘0’.
Transmit Shift Direction (Bit 25). TSD controls the shift direction of transmit shift register (TxSR). Transmit data is
transmitted MSB first when TSD = ‘0’ or LSB first otherwise. The operation of this bit is explained in more detail in
section 17.8.
Receive Shift Direction (Bit 24). The RSD bit value should only be changed when the receiver is disabled. RSD con-
trols the shift direction of receive shift register (RxSR). Receive data is received MSB first when RSD = ‘0’, LSB first
otherwise. The operation of this bit is explained in more detail in section 17.8.
Mode Select SSI_IO1 pin (Bit 23-22). The IO1 field value should only be changed when the transmitter and receiver
are disabled. The IO1[1:0] bits are used to select the function of SSI_IO1 pin. The function may be selected as listed
in table
Mode Select SSI_IO2 pin (Bit 21-20). The IO2 field value should only be changed when the transmitter and receiver
are disabled. The IO2[1:0] bits are used to select the function of SSI_IO2 pin. The function may be selected according
to
Write IO1 (Bit 19). Value written here appears on the SSI_IO1 pin when the pin is configured to be a general purpose
output.
Write IO2 (Bit 18). Value written here appears on the SSI_IO2 pin when this pin is configured to be a general purpose
output.
Transmit Interrupt Enable (Bit 17). Enables interrupt by the TDE flag in the SSI status register (transmit needs refill)
Also enables interrupt of the TUE (transmitter underrun error) and TXFES (transmit framing error)
Receive Interrupt Enable (Bit 16). When RIE is set, the DSPCPU will be interrupted when RDF in the SSI status reg-
ister is set (receive complete). It will also be interrupted on ROE (receiver overrun error) and on RXFES (receive
framing error).
Frame Size Select (Bits 15-12). The FSS[3:0] bits control the divide ratio for the programmable frame rate divider
used to generate the frame sync pulses. The valid setup value ranges from 1 to 16 slot(s). The value ‘16’ is accom-
plished by storing a 0 in this field.
Table 17-7
Table
17-6.
Description
PRELIMINARY SPECIFICATION
Synchronous Serial Interface
17-9