PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 160

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Table 10-3
DSPCPU clock combinations:
Table 10-3. SPDIF sample rate setting
The programmer is free to change FREQUENCY, and
hence the system sample rate to perform long-term
tracking of any absolute timing source and/or control
software buffer fullness. Changes to the FREQUENCY
register pull-in or delay the next clock edge and have no
instantaneous effect on clock level, i.e. the rate of phase
progression is changed, not the phase.
10.9
When SPDO is set to operate in transparent mode, it
takes all 32 bits of the memory data and shifts them out
verbatim, without bi-phase mark encoding, parity gener-
ation, or preamble.
Two transparent modes are provided, as determined by
TRANS_MODE in SPDO_CTL: LSB first and MSB first.
One bit of memory data is transmitted for each DDS
clock, such that the FREQUENCY register value for a
desired bitrate is given by the following equation:
The 32-bit memory word is constructed according to the
same rules for LITTLE_ENDIAN as in
“IEC-958 Memory Data Format.”
10.10 DMA OPERATION
Before enabling the SPDO block, software must assign
two buffers with data to SPDO_BASE1, SPDO_BASE2,
and SPDO_SIZE (buffer size in bytes). Each memory
buffer size must be a multiple of 64 bytes regardless of
the operating mode.
The SPDO block is enabled by writing a ‘1’ to
SPDO_CTL.TRANS_ENABLE. Once enabled, the first
DMA buffer is sent out at the programmed sample rate.
Once the first buffer is empty, BUF1_ACTIVE is negated,
10-4
32.000
32.000
32.000
44.100
44.100
44.100
48.000
48.000
48.000
(kHz)
FREQUENCY
f
jitter
s
TRANSPARENT MODE
f
shows settings for common sample rate and
=
DSPCPU
(MHz)
143
166
180
143
166
180
143
166
180
---------------------------- -
9 f
⋅
DSPCPU
1
0x80D0,9316
0x80B3,ACF8
0x80A5,B36E
0x811F,711B
0x80F7,9D93
0x80E4,5B47
0x8138,DCA1
0x810D,8375
0x80F8,8D25
(hexadecimal)
FREQUENCY
=
PRELIMINARY SPECIFICATION
2
31
+
2
----------------------------- -
9 f
32
⋅
⋅
DSPCPU
244.14 0.777
244.14 0.669
244.14 0.617
177.15 0.777
177.15 0.669
177.15 0.617
162.76 0.777
162.76 0.669
162.76 0.617
(nSec)
bitrate
UI
Section 10.7,
(nSec)
jitter
Eq. 2
a timestamp is generated (see
tamps”) and the BUF1_EMPTY flag in SPDO_STATUS
is asserted. If BUF1_INTEN in SPDO_CTL is also as-
serted, an interrupt to the DSPCPU is generated. The
SPDO block continues emitting the data in DMA buffer 2.
In normal operation, the DSPCPU assigns a new buffer
1 full of data to SPDO and signals this by writing a ‘1’ to
ACK_BUF1. The SPDO block immediately negates the
BUF1_EMPTY condition and the related interrupt re-
quest. Once buffer 2 is empty, similar signaling occurs
and the hardware switches back to using buffer 1.
10.11 DMA ERROR CONDITIONS
Two types of error can occur during DMA operation.
If the software fails to provide a new buffer of data in
time, and both DMA buffers empty out, the SPDO hard-
ware raises the UNDERRUN flag in SPDO_STATUS.
Transmission switches over to the use of the next buffer,
but the data transmitted is incorrect. If UDR_INTEN is
asserted, an interrupt will be generated. The UNDER-
RUN flag is sticky, i.e. it will remain asserted until the
software clears it by writing a ‘1’ to ACK_UDR.
A lower level error can also occur when the limited size
internal buffer empties out before it can be refilled across
the highway. This situation can arise only if insufficient
bandwidth has been requested from the highway. In this
case, the HBE error flag is raised. Refer to
“HBE and Highway Latency”
set the arbiter latency correctly.
10.12 INTERRUPTS
The SPDO block uses interrupt SRC NUM 25, with inter-
rupt vector MMIO offset 0x1008E4.
It is highly recommended that the interrupt be operated
in level-sensitive mode only.
The SPDO block generates an interrupt if one of the fol-
lowing status bit flags, and its corresponding INTEN_xxx
flag are set: BUF1_EMPTY, BUF2_EMPTY, HBE, UN-
DERRUN.
All these status flags are sticky, i.e. they are asserted by
hardware when a certain condition occurs, and remain
set until the interrupt handler explicitly clears them by
writing a ‘1’ to the corresponding ACK bit in SPDO_CTL.
The SPDO hardware takes the flag away in the clock cy-
cle after the ACK is received. This allows immediate re-
turn from interrupt once performing an ACK.
10.13 TIMESTAMPS
Any outgoing DMA buffer is assigned a 32-bit ‘time of de-
parture’ timestamp. The counter used to generate times-
tamps uses the DSPCPU clock and the same reset time
as the DSPCPU CCCOUNT register, resulting in a value
that corresponds to the 32 LSB’s of CCCOUNT - provid-
ed that PCSW.CS=1, i.e. the real CCCOUNT counter in-
crements on every clock cycle.
Philips Semiconductors
for a description of how to
Section 10.13, “Times-
Section 10.17,