PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 275

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

Arbiter
20.1
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The PNX1300 internal highway bus conveys all the
memory and MMIO traffic. The on-chip peripheral units
described in this databook are connected to this internal
highway bus. Accesses to the bus are controlled by a
central arbiter.
system where the arbiter is embedded in the main mem-
ory interface (MMI) block. The traffic includes the memo-
ry requests issued by most of the on-chip units as well as
the MMIO transactions issued by the DSPCPU or PCI
block and responded to by the peripherals.
The arbiter was designed to make PNX1300 a true real-
time system by providing a highly programmable bus
bandwidth allocation scheme. The primary characteris-
tics are:
• round robin arbitration
• hierarchical organization
• programmable allocation of highway bandwidth
• dual priorities with priority raising mechanism
These features are explained in the next sections of this
chapter. The arbiter is programmed through two MMIO
registers:
• ARB_RAISE
• ARB_BW_CTL
The default values (after hardware RESET) stored in
these two MMIO registers are suitable for most of the ap-
plications. If these default settings introduce violations of
real-time constraints in units like Video In (VI), Video Out
(VO), Audio In (AI) and Audio Out (AO) (each of these
units has a Highway Bandwidth Error detection mecha-
nism), the ARB_BW_CTL register should be pro-
grammed to 0x090A9. This setting gives almost maxi-
mum priority to real-time units but may slow down the
CPU.
Fine tuning of the arbiter settings is described in the fol-
lowing sections.
20.2
The best CPU performance is obtained if cache misses
can take priority over peripheral requests on the high-
way. However, peripherals need to have a maximum
ARBITER FEATURES
DUAL PRIORITIES WITH PRIORITY
RAISING MECHANISM
Figure 2-1 on page 2-2
by Eino Jacobs, Luis Lucas, Chris Nelson, Allan Tzeng, Gert Slavenburg
shows the whole
guaranteed latency low enough to satisfy the real-time
constraints of I/O units.
PNX1300 provides this feature with the following priority-
raising mechanism.
Peripheral unit requests can have 2 priorities: low and
high. Within each class there is fair, round-robin arbitra-
tion
cedence over requests with low priority.
Units can indicate the priority of their requests to be low
or high.
A unit may initially post a request with low priority. If the
request is not serviced within a particular waiting time,
the unit can raise the priority of the request to high. This
can be done when the worst case latency at high priority
approaches the real-time constraint of the unit. Thus, the
unit uses only spare bandwidth without slowing down the
CPU unless real-time constraints require it to claim high
priority.
In PNX1300, only the ICP unit has its own priority raising
logic (i.e. it controls the low to high transition of the re-
quest). Refer to
more information.
Priority raising for the VLD, PCI, VI and VO units is han-
dled by the arbiter central priority raising mechanism.
The central priority raising mechanism settings are con-
trolled from the DSPCPU with the ARB_RAISE MMIO
register (see
time for which the arbiter handles the request at low pri-
ority.
The delay is defined by a 5-bit field (dedicated per unit)
and is counted in CPU clock cycles. The granularity of
the delay is 16 cycles, so the maximum time spent at low
priority for each request can be programmed from 0 to
496 cycles, inclusive, in increments of 16 cycles.
Table 20-1. ARB_RAISE register layout
The default value for the entire ARB_RAISE register is
‘0’. This causes all requests from VLD, PCI, VI and VO to
be
PRELIMINARY SPECIFICATION
0x10010C
Offset
(Section
handled
20.3). Requests with high priority take pre-
ARB_RAISE
Table
as
Name
Chapter 14, “Image Coprocessor,”
20-1). The delay is the amount of
high-priority
19:15
14:10
Bits
9:5
4:0
Chapter 20
requests
VLD_delay[4:0]
PCI_delay[4:0]
Fields
VO_delay[4:0]
VI_delay[4:0]
until
20-1
the
for