PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 171

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Table 11-6. Base Class Encodings
Table 11-7. Subclass & programming interface fields
11.5.7
This field only matters when the MWI bit in configuration
space is set. The value of the Cache Line Size register
specifies the host system cache line size in units of 32-
bit words. Initiating devices, such as the PNX1300, that
can generate memory-write-and-invalidate commands
must implement this register. When implemented, the
cache line size allows initiators participating in the PCI
caching protocol to retry burst accesses at cache-line
boundaries.
This register is implemented in PNX1300. In the
PNX1300, PCI DMA performs write-and-invalidate cy-
cles as per the table below. ICP DMA and CPU PCI
writes are performed using normal memory-write cycles.
Table 11-8. Cache line size values
Cache Line Size
0000,0100
0000,1000
0001,0000
all other values
Base Class
Subclass
(in hex)
(in hex)
0D–FE
00
01
80
(binary)
0A
0B
0C
FF
00
01
02
03
04
05
06
07
08
Cache Line Size Register
Interface (in hex)
Device was built before class code definitions
were finalized
Mass-storage controller
Network controller
Display controller
Multimedia device
Memory controller
Bridge device
Simple communications controller
Base system peripheral
Docking station
Processor
Serial bus controller
Reserved
Device does not fit any of the above classes
Programming
write-and-invalidates are done in 4-
DWORD, i.e. 16-byte chunks
write-and-invalidate in 8-DWORD chunks
write-and-invalidate in 16-DWORD chunks
only normal ‘memory-write’ is performed
00
00
00
Video device
Audio device
Other multimedia device
Meaning
Effect
Meaning
Figure 11-6. Header type register format.
11.5.8
The value of the Latency Timer register specifies the
minimum number of PCI clock cycles the PNX1300 BIU
(as initiator) is allowed to own the PCI bus. This register
is readable and writable in PCI configuration space.
This register must be writable in any PCI-initiating device
that can burst more than two data phases. In the
PNX1300 PCI interface, the least-significant three bits
are hardwired to ’0’ and software can program any value
into the most-significant five bits. This permits software
to specify the time slice with a minimum granularity of
eight PCI clocks. A value of ’0’ signifies maximum laten-
cy, i.e. 256 PCI clocks.
11.5.9
The value of the Header Type register defines the format
of words 16 through 63 in configuration space and
whether or not the device contains multiple functions.
Figure 11-6
Bit 7 of Header Type is ’0’ for single-function devices, ’1’
for multi-function devices. PNX1300 is a single-function
device, so bit 7 is ’0’.
the Layout field.
Table 11-9. Layout encodings
11.5.10 Built-In Self Test Register
When implemented, the BIST register is used to control
the operation of a device’s built-in self testing capability.
PNX1300 does not implement BIST, so this register is
hardwired to return ’0’s when read.
11.5.11 Base Address Registers
The PNX1300 PCI interface implements two configura-
tion
DRAM_BASE and MMIO_BASE. DRAM_BASE relo-
cates PNX1300’s SDRAM within the system address
space; MMIO_BASE relocates the 2-MB memory-
mapped I/O address aperture.
The values in the Base Address registers determine the
address map as seen by both the DSPCPU and external
PCI masters. These values are normally set once, and
not changed dynamically once the DSPCPU operates.
PRELIMINARY SPECIFICATION
Header Type
Layout (in hex)
space
Latency Timer Register
Header Type Register
00
01
shows the format of Header Type.
memory
MF
7
Table 11-9
6
Non-bridge PCI device
PCI-to-PCI bridge device
Base
shows the encodings of
Layout
Meaning
Address
PCI Interface
registers:
11-7
0