PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 221

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
14.5.7
Figure 14-11
horizontal scaling algorithm implementation. Blocks of
pixels are provided by the input block buffer. Each block
of pixels is transferred sequentially to the 5-tap filter. The
filter does scaling and filtering of the data and puts the re-
sulting pixels in the output buffer. Completed pixels in the
output buffer are written back to SDRAM or to the PCI
output. A bypass multiplexer allows the filter to be by-
passed for SDRAM to SDRAM block moves.
Input pixel access is controlled by the Y Counter. The Y
Counter selects the word and byte for the current pixel in
the Y FIFO buffer. The Y Increment register, Y LSB Reg-
ister and the Y MSB Counter control the increment of the
Y Counter. If the Y MSB Counter contents is not ‘0’, the
Y Counter is incremented and the Y MSB register is dec-
remented until the Y MSB Counter is ‘0’.
The Y MSB Counter is loaded with the integer portion of
the results of the Y Counter Increment operation. Y
Counter Increment involves adding the Y Increment frac-
tion and integer values to the Y LSB register and Y MSB
Counter, respectively. If there is no scaling (scaling fac-
tor = 1.0), the Y Increment integer value will be ‘1’, and
the Y Increment fractional value will be ‘0’.
Counter Increment operation will increment the Y
Counter by one in this case.
Figure 14-11. ICP horizontal scaling data flow block diagram
Address
SDRAM
Pixel Clock
SDRAM
highway
N Byte Incr
Block
via
Implementation Overview: Horizontal
Scaling and Filtering
shows a data flow block diagram of the ICP
Y Incr Integer
Y MSB Cntr
Y Counter
Buffers 0,1
Block FIFO
Carry Out
Y Incr Fraction
Y LSB Reg
Filter Source Select
Each Y
5 Stage Multipli-
er-Accumulator
Y LSBs
Bypass
5-tap Filter
The Y Counter keeps track of horizontally indexed pixels
sent to the filter. The Y Counter is incremented once (1.0
for no scaling) for each pixel. For a line of pixels begin-
ning with X
els from the block buffer beginning with X
with X
which uses a total of 5 pixels to generate each output pix-
el, two pixels before and two pixels after each pixel. The
horizontal filter uses the current output from the block
buffer and four delayed versions of it to generate the filter
output as the weighted sum of the center pixel plus the
two on either side. (For the case where the scaling factor
= 1.0, the LSBs are always ‘0’.)
For up or down scaling, the Y Increment value is not 1.0,
it is the inverse of the scaling factor (See
output resolution,” on page
factor of 2.0, the effective Y increment value is 0.5, for
example. This means two output pixels are generated for
each input pixel. The Y Counter effectively increments as
0.0, 0.5, 1.0, 1.5, 2.0, etc. The LSBs of the counter (i.e.
the fractional part less than 1) in the Y LSB register are
used by to the filter to generate the intermediate values.
An LSB value of 0.5 indicates that the output pixel is half
way between X
filter parameter RAMs, one for each coefficient. The 5
most significant LSBs from the counter select the filter
coefficients which will generate the correct value for the
output pixel at the relative offset from 0.0 indicated by the
LSBs.
PRELIMINARY SPECIFICATION
YUV Code Delay
b+2
. The extra pixels are required by the 5-tap filter,
a
and ending with X
Bypass
n
and X
n+1
Output
Buffers 6,7
Block FIFO
. The filter contains a set of 5
14-7). For up scaling by a
b
Z Counter
, the Y Counter reads pix-
Image Coprocessor
a-2
“ICP scaling
and ending
14-11