PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 241

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
The VLD reads data from SDRAM into an internal 64-
byte FIFO. The VLD processing engine then reads data
from the FIFO as needed. Once this internal FIFO is
empty the VLD reads more data from SDRAM. The
VLD_BIT_ADR and VLD_BIT_CNT registers are updat-
ed after each read from main memory. The content of the
VLD_BIT_ADR register reflects the next address from
which the bitstream data will be fetched. The content of
the VLD_BIT_CNT register reflects the number of bytes
remaining to be read before the current transfer is com-
plete. When the number of bytes remaining to be read
from SDRAM is zero, a status flag is set and an interrupt
can be generated to the DSPCPU. The DSPCPU will
provide the new bitstream buffer address and the num-
ber of bytes in the bitstream buffer to the VLD.
Table 15-1. References for the MPEG-2 macroblock
header data
Esc count
MBA inc
MB type
Mot type
DCT type
MV count
MV format
DMV
MV field Sel[0]0] to
MV field Sel[1][1]
Motion
code[0][0][0] to
Motion
code[1][1][1]
Motion Resid-
ual[0][0][0] to
Motion Resid-
ual[1][1][1]
dmvector[1] and
dmvector[0]
CBP
Quant scale
Item
Default
value
unde-
unde-
unde-
unde-
unde-
unde-
unde-
unde-
unde-
unde-
fined
fined
fined
fined
fined
fined
fined
fined
fined
fined
0
-
-
-
Section 6.2.5
Section 6.2.5 and Table B-1
Section 6.2.5.1 and Tables B-
2, B-3, and B-4; Only 5 Msb
bits from the tables are used
Section 6.2.5.1; Field or Frame
motion type will be decided by
the user
Section 6.2.5.1
Tables 6-17 and 6-18. The MV
Count value is one less than
the value from the tables.
Tables 6-17 and 6-18
Tables 6-17 and 6-17
Section 6.2.5 and 6.2.5.2
Section 6.2.5.2.1 and
Table B-10
Section 6.2.5.2.1; the corre-
sponding rsize bits are
extracted from the bitstream
and stored as left justified; to
get the final value shift the
given number by 8 (corre-
sponding rsize). The rsize val-
ues are stored in VLD_PI
register
Section 6.2.5.2.1 and Table B-
11; signed 2-bit integer from
Table B11.
Section 6.2.5, 6.2.5.3 and
Table B-9
Section 6.2.5; 5-bit from bit-
stream and use Table 7-6 to
compute the quant scale value.
Video Standard, IS 13818-2
References from MPEG-2
document
15.5
The VLD outputs two data streams which are written
back to main memory by two output DMA engines.
These DMA engines are programmed by the DSPCPU.
One of the output streams contains macroblock header
information and the other contains run-length encoded
DCT coefficients. Each DMA engine contains a 64-byte
FIFO which is transferred to main memory once it is full.
The main memory address and count for the macroblock
header output are contained in the VLD_MBH_ADR and
VLD_MBH_CNT registers respectively. The main mem-
ory address and count for the DCT coefficient output are
contained in the VLD_RL_ADR and VLD_RL_CNT reg-
isters respectively. The counts for both the macroblock
header and coefficient data are expressed in terms of 32-
bit (4 bytes) words.
15.5.1
For each MPEG-2 macroblock parsed by the VLD, six
32-bit words of macroblock header information will be
output from the VLD.
the VLD output, the fields are described in
Note that these fields may or may not be valid depending
upon the MPEG-2 video standard[2]. For example, mo-
tion vectors are not valid for intra coded macroblocks.
Similarly, ‘DCT Type’ is not valid for field pictures.
For each MPEG-1 macroblock parsed by the VLD, four
32-bit words of macroblock header information will be
output from the VLD.
the VLD output, while the fields are described in
Table
id depending upon the MPEG-1 video standard[1].
Table 15-2. References for the MPEG-1 macroblock
header data
PRELIMINARY SPECIFICATION
Esc count
MBA inc
MB type
Motion
code[0][0][0] to
Motion
code[0][1][1]
Motion resid-
ual[0][0][0] to
Motion resid-
ual[0][1][1]
CBP
Quant scale
15-2. Note that these fields may or may not be val-
Item
VLD OUTPUT
Macroblock Header Output Data
Default
value
unde-
unde-
unde-
fined
fined
fined
Figure 15-2
Figure 15-3
0
-
-
-
Variable Length Decoder
Section 2.4.3.6
Section 2.4.3.6
Section 2.4.3.6 and Tables B-
2a to B2d
Section 2.4.2.7 and Table B-4
Section 2.4.2.7;the corre-
sponding rsize bits are
extracted from the bitstream
and stored as left justified; to
get the final value shift the
given number by (8 - corre-
sponding rsize). The rsize val-
ues are stored in VLD_PI
register.
Section 2.4.3.6 and Table B-3
Section 2.4.2.7
References from IS 11172-2
pictures the layout of
pictures the layout of
document
Table
15-1.
15-3