MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 82

• Manufacturer Part Number: MC9S08AW32CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW32CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6 Parallel Input/Output
6.3
The MC9S08AW60 Series has a total of 54 parallel I/O pins in seven ports (PTA–PTG). Not all pins are
bonded out in all packages. Consult the pin assignment in
parallel I/O pins. All of these pins are available for general-purpose I/O when they are not used by other
on-chip peripheral systems.
After reset, the shared peripheral functions are disabled so that the pins are controlled by the parallel I/O.
All of the parallel I/O are configured as inputs (PTxDDn = 0). The pin control functions for each pin are
configured as follows: slew rate control enabled (PTxSEn = 1), low drive strength selected (PTxDSn = 0),
and internal pullups disabled (PTxPEn = 0).
The following paragraphs discuss each port and the software controls that determine each pin’s use.
6.3.1
Port A pins are general-purpose I/O pins. Parallel I/O function is controlled by the port A data (PTAD) and
data direction (PTADD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTAPE), slew rate control (PTASE), and drive strength select (PTADS) are located in the
high page registers. Refer to
general-purpose I/O control and
6.3.2
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Port A
Port B
Software-controlled slew rate output buffers
Eight port A pins
Eight port B pins shared with ADC1
Seven port C pins shared with SCI2, IIC1, and MCLK
Eight port D pins shared with ADC1, KBI1, and TPM1 and TPM2 external clock inputs
Eight port E pins shared with SCI1, TPM1, and SPI1
Eight port F pins shared with TPM1 and TPM2
Seven port G pins shared with XTAL, EXTAL, and KBI1
Pin Descriptions
Port A
Port B
MCU Pin:
MCU Pin:
AD1P7
PTB7/
PTA7
Section 6.4, “Parallel I/O
Bit 7
Bit 7
Section 6.5, “Pin
AD1P6
PTB6/
PTA6
Figure 6-1. Port A Pin Names
Figure 6-2. Port B Pin Names
MC9S08AW60 Data Sheet, Rev 2
6
6
AD1P5
PTB5/
PTA5
5
5
Control” for more information about pin control.
Control” for more information about
AD1P4
PTB4/
PTA4
Chapter 2, “Pins and
4
4
AD1P3
PTB3/
PTA3
3
3
AD1P2
PTB2/
PTA2
2
2
Connections,” for available
AD1P1
PTB1/
PTA1
Freescale Semiconductor
1
1
AD1P0
PTB0/
PTA0
Bit 0
Bit 0