MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 300

• Manufacturer Part Number: MC9S08AW32CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW32CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Appendix A Electrical Characteristics and Timing Specifications
A.10
This section describes ac timing characteristics for each peripheral system. For detailed information about
how clocks for the bus are generated, see
A.10.1
300
1
2
3
4
5
Num
Typical values are based on characterization data at V
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on
the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% V
1
2
4
6
8
3
5
7
9
AC Characteristics
C
P
T
Control Timing
Bus frequency (t
Real-time interrupt internal oscillator period
External reset pulse width
(t
Reset low drive
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ pulse width
KBIPx pulse width
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
cyc
Asynchronous path
Synchronous path
Asynchronous path
Synchronous path
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
Slew rate control enabled (PTxSE = 1)
Slew rate control disabled (PTxSE = 0)
= 1/f
Self_reset
3
cyc
)
Parameter
= 1/f
4
3
2
2
Bus
DD
2
)
MC9S08AW60 Data Sheet, Rev 2
and 80% V
Table A-13. Control Timing
Chapter 8, “Internal Clock Generator
DD
DD
levels. Temperature range –40°C to 125°C.
= 5.0V, 25°C unless otherwise stated.
5
t
t
t
t
Symbol
Rise
Rise
ILIH,
ILIH,
t
t
t
MSSU
t
rstdrv
f
extrst
t
MSH
Bus
RTI
, t
, t
t
t
IHIL
IHIL
Fall
Fall
t
1.5 x t
1.5 x t
34 x t
Self_reset
1.5 x
Min
700
100
100
dc
25
25
—
—
—
—
cyc
cyc
cyc
(S08ICGV4).”
Typ
—
—
—
40
75
11
35
1
Freescale Semiconductor
1300
Max
20
—
—
—
—
—
—
—
—
—
—
MHz
Unit
μs
ns
ns
ns
ns
ns
ns
ns
ns