MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 222
MC9S08AW32CFGE
Manufacturer Part Number
MC9S08AW32CFGE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08AW32CFGE.pdf
(324 pages)
Specifications of MC9S08AW32CFGE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
34
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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Chapter 13 Inter-Integrated Circuit (S08IICV1)
13.3.3
222
Reset
IICEN
TXAK
RSTA
Field
IICIE
MST
TX
7
6
5
4
3
2
W
R
IICEN
IIC Control Register (IIC1C)
IIC Enable — The IICEN bit determines whether the IIC module is enabled.
0 IIC is not enabled.
1 IIC is enabled.
IIC Interrupt Enable — The IICIE bit determines whether an IIC interrupt is requested.
0 IIC interrupt request not enabled.
1 IIC interrupt request enabled.
Master Mode Select — The MST bit is changed from a 0 to a 1 when a START signal is generated on the bus
and master mode is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode
of operation changes from master to slave.
0 Slave Mode.
1 Master Mode.
Transmit Mode Select — The TX bit selects the direction of master and slave transfers. In master mode this bit
should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high.
When addressed as a slave this bit should be set by software according to the SRW bit in the status register.
0 Receive.
1 Transmit.
Transmit Acknowledge Enable — This bit specifies the value driven onto the SDA during data acknowledge
cycles for both master and slave receivers.
0 An acknowledge signal will be sent out to the bus after receiving one data byte.
1 No acknowledge signal response is sent.
Repeat START — Writing a one to this bit will generate a repeated START condition provided it is the current
master. This bit will always be read as a low. Attempting a repeat at the wrong time will result in loss of arbitration.
0
7
= Unimplemented or Reserved
IICIE
0
6
Table 13-4. IIC1C Register Field Descriptions
Figure 13-5. IIC Control Register (IIC1C)
MST
0
5
MC9S08AW60 Data Sheet, Rev 2
TX
0
4
Description
TXAK
3
0
RSTA
0
0
2
Freescale Semiconductor
0
0
1
0
0
0
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