MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 80

• Manufacturer Part Number: MC9S08AW32CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW32CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

1
2
Chapter 5 Resets, Interrupts, and System Configuration
5.9.9
This register is used to report the status of the low voltage warning function, and to configure the stop mode
behavior of the MCU.
80
Power-on
Any other
This bit can be written only one time after reset. Additional writes are ignored.
LVWF will be set in the case when V
LVWACK
PPDACK
reset:
reset:
reset:
PPDC
LVWF
LVWV
PPDF
Field
LVDV
LVD
7
6
5
4
3
2
0
W
R
System Power Management Status and Control 2 Register (SPMSC2)
LVWF
0
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
0
0
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge.
Writing a 1 to LVWACK clears LVWF to a 0 if a low voltage warning is not present.
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode.
0 Not stop2 mode recovery.
1 Stop2 mode recovery.
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
Partial Power Down Control — The write-once PPDC bit controls whether stop2 or stop3 mode is selected.
0 Stop3 mode enabled.
1 Stop2, partial power down, mode enabled.
(2)
7
(2)
(2)
= Unimplemented or Reserved
LVWACK
0
0
0
0
6
Table 5-12. SPMSC2 Register Field Descriptions
Supply
LVD
LVW
LVDV
LVD
LVW
transitions below the trip point or after reset and V
U
U
0
5
MC9S08AW60 Data Sheet, Rev 2
= V
= V
= V
= V
LVDL
LVWL
LVDH
LVWH
).
).
).
).
LVWV
U
U
0
4
Description
PPDF
3
0
0
0
PPDACK
U = Unaffected by reset
0
0
0
0
2
Supply
is already below V
Freescale Semiconductor
0
0
0
1
LVD
LVW
).
).
PPDC
0
0
0
0
LVW
1
.