MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 123

• Manufacturer Part Number: MC9S08AW32CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW32CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
CPX #opr8i
CPX opr8a
CPX opr16a
CPX oprx16,X
CPX oprx8,X
CPX ,X
CPX oprx16,SP
CPX oprx8,SP
DAA
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ oprx8,SP,rel
DEC opr8a
DECA
DECX
DEC oprx8,X
DEC ,X
DEC oprx8,SP
DIV
EOR #opr8i
EOR opr8a
EOR opr16a
EOR oprx16,X
EOR oprx8,X
EOR ,X
EOR oprx16,SP
EOR oprx8,SP
INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP
JMP opr8a
JMP opr16a
JMP oprx16,X
JMP oprx8,X
JMP ,X
JSR opr8a
JSR opr16a
JSR oprx16,X
JSR oprx8,X
JSR ,X
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
LDHX #opr16i
LDHX opr8a
LDHX opr16a
LDHX ,X
LDHX oprx16,X
LDHX oprx8,X
LDHX oprx8,SP
Source
Form
Compare X (Index
Register Low) with
Memory
Decimal Adjust
Accumulator After ADD or
ADC of BCD Values
Decrement and Branch if
Not Zero
Decrement
Exclusive OR
Memory with
Accumulator
Increment
Jump to Subroutine
Load Accumulator from
Memory
Load Index Register (H:X)
from Memory
Divide
Jump
Operation
Table 7-2. HCS08 Instruction Set Summary (Sheet 4 of 7)
Push (PCH); SP ← (SP) – 0x0001
Push (PCL); SP ← (SP) – 0x0001
MC9S08AW60 Data Sheet, Rev 2
(CCR Updated But Operands Not
PC ← (PC) + n (n = 1, 2, or 3)
PC ← Unconditional Address
DBNZX Affects X Not H
H:X ← (M:M + 0x0001)
Decrement A, X, or M
PC ← Jump Address
Branch if (result) ≠ 0
M ← (M) + 0x01
M ← (M) + 0x01
M ← (M) + 0x01
M ← (M) + 0x01
M ← (M) – 0x01
M ← (M) – 0x01
M ← (M) – 0x01
M ← (M) – 0x01
H ← Remainder
A ← (A) – 0x01
X ← (X) – 0x01
A ← (A) + 0x01
X ← (X) + 0x01
A ← (H:A)÷(X)
Description
A ← (A ⊕ M)
Changed)
(X) – (M)
A ← (M)
(A)
10
V H I N Z C
U – –
– – – – – –
– – – –
0 – –
– – – – – –
– – – – – –
0 – –
0 – –
↕
↕
↕
– –
– –
– –
Chapter 7 Central Processor Unit (S08CPUV2)
on CCR
Effect
↕ ↕ ↕
↕ ↕ ↕ INH
↕ ↕
↕ ↕
↕ ↕
↕ ↕
↕ ↕
↕ ↕ INH
–
–
–
–
–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
INH
INH
IX1
IX
SP1
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
IMM
DIR
EXT
IX
IX2
IX1
SP1
9ECE
9EAE
9EBE
9ED3
9EE3
9E6B
9E6A
9ED8
9EE8
9E6C
9ED6
9EE6
9EFE
CC
DC
CD
DD
BC
EC
FC
BD
ED
FD
C3
D3
C8
D8
3C
4C
5C
6C
7C
C6
D6
A3
B3
E3
3B
4B
5B
6B
7B
3A
4A
5A
6A
7A
A8
B8
E8
A6
B6
E6
F3
72
52
F8
F6
45
55
32
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd rr
rr
rr
ff
rr
ff
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
jj
dd
hh ll
ee ff
ff
ff
rr
rr
kk
2
3
4
4
3
3
5
4
1
7
4
4
7
6
8
5
1
1
5
4
6
6
2
3
4
4
3
3
5
4
5
1
1
5
4
6
3
4
4
3
3
5
6
6
5
5
2
3
4
4
3
3
5
4
3
4
5
5
6
5
5
123