ISP1508BET STEricsson, ISP1508BET Datasheet - Page 85

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
27. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Single and back-to-back RXCMDs from the
Fig 11. RXCMD A_VBUS_VLD indicator source . . . . . . .32
Fig 12. Example of register write, register read, extended
Fig 13. USB reset and high-speed detection handshake
Fig 14. Example of using the ISP1508 to transmit and
Fig 15. High-speed transmit-to-transmit packet timing. . .38
Fig 16. High-speed receive-to-transmit packet timing . . .39
Fig 17. Preamble sequence . . . . . . . . . . . . . . . . . . . . . . .40
Fig 18. Full-speed suspend and resume . . . . . . . . . . . . .41
Fig 19. High-speed suspend and resume . . . . . . . . . . . .43
Fig 20. Remote wake-up from low-power mode . . . . . . .45
Fig 21. Transmitting USB packets without automatic SYNC
Fig 22. Example of transmit followed by receive in 6-pin
Fig 23. Example of transmit followed by receive in 3-pin
Fig 24. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .69
Fig 25. Timing of TX_DAT and TX_SE0 to DP and DM . .69
Fig 26. Timing of TX_ENABLE to DP and DM. . . . . . . . .69
Fig 27. Timing of DP and DM to RX_RCV, RX_DP and
Fig 28. ULPI timing interface . . . . . . . . . . . . . . . . . . . . . .69
Fig 29. ISP1508 in peripheral only application. . . . . . . . .71
Fig 30. ISP1508 in OTG application . . . . . . . . . . . . . . . .72
Fig 31. ISP1508 in host application . . . . . . . . . . . . . . . . .73
Fig 32. Package outline SOT912-1 (TFBGA36). . . . . . . .74
Fig 33. Temperature profiles for large and small
ISP1508A_ISP1508B_2
Product data sheet
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .5
V
Digital overcurrent detection scheme. . . . . . . . . .16
Internal power-on reset timing . . . . . . . . . . . . . . .17
Power-up and reset sequence required before the
ULPI bus is ready for use. . . . . . . . . . . . . . . . . . .18
Interface behavior with respect to the CHIP_SEL
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Interface behavior when entering UART mode . .26
Interface behavior when exiting UART mode . . . .26
ISP1508 to the link. . . . . . . . . . . . . . . . . . . . . . . .30
register write and extended register read . . . . . .34
(chirp) sequence . . . . . . . . . . . . . . . . . . . . . . . . .36
receive USB data . . . . . . . . . . . . . . . . . . . . . . . . .37
and EOP generation . . . . . . . . . . . . . . . . . . . . . .46
serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
BUS
pin internal pull-up and pull-down scheme .10
Rev. 02 — 13 March 2008
ISP1508A; ISP1508B
ULPI HS USB OTG transceiver
© NXP B.V. 2008. All rights reserved.
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