ISP1508BET STEricsson, ISP1508BET Datasheet - Page 57

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 39.
Table 40.
Table 41.
ISP1508A_ISP1508B_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
Symbol
-
ID_GND
SESS_END
SESS_VALID
VBUS_VALID
HOST_DISCON
USB Interrupt Status register (address R = 13h) bit allocation
USB Interrupt Status register (address R = 13h) bit description
USB Interrupt Latch register (address R = 14h) bit allocation
11.7 USB Interrupt Status register
11.8 USB Interrupt Latch register
X
R
R
7
7
0
This register (see
The bits of the USB Interrupt Latch register are automatically set by the ISP1508 when an
unmasked change occurs on the corresponding interrupt source signal. The ISP1508 will
automatically clear all bits when the link reads this register, or when the PHY enters
low-power mode.
Remark: It is optional for the link to read this register when the clock is running because
all signal information will automatically be sent to the link through the RXCMD byte.
The bit allocation of this register is given in
reserved
reserved
R
R
X
Description
reserved
ID Ground: Reflects the current value of the ID detector circuit.
Session End: Reflects the current value of the session end voltage comparator.
Session Valid: Reflects the current value of the session valid voltage comparator.
V
Host Disconnect: Reflects the current value of the host disconnect detector.
6
6
0
BUS
Valid: Reflects the current value of the V
Table
X
R
R
5
5
0
Rev. 02 — 13 March 2008
39) indicates the current value of the interrupt source signal.
ID_GND_L
ID_GND
R
R
4
0
4
0
SESS_
SESS_
END_L
Table
END
R
R
3
0
3
0
ISP1508A; ISP1508B
BUS
41.
valid voltage comparator.
VALID_L
SESS_
SESS_
VALID
ULPI HS USB OTG transceiver
R
R
2
0
2
0
VALID_L
VBUS_
VBUS_
VALID
R
R
1
0
1
0
© NXP B.V. 2008. All rights reserved.
DISCON_L
DISCON
HOST_
HOST_
R
R
0
0
0
0
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