ISP1508BET STEricsson, ISP1508BET Datasheet - Page 50

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1508A_ISP1508B_2
Product data sheet
10.11 Aborting transfers
10.12 Avoiding contention on the ULPI data bus
The ISP1508 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4.
Because the ULPI data bus is bidirectional, avoid situations in which both the link and the
PHY simultaneously drive the data bus.
The following points must be considered while implementing the data bus drive control on
the link.
After power-up and clock stabilization, default states are as follows:
When the ISP1508 wants to take control of the data bus to initiate a data transfer, it
changes the DIR value from LOW to HIGH.
At this point, the link must disable its output buffers. This must be as fast as possible so
the link must use a combinational path from DIR.
The ISP1508 will not immediately enable its output buffers, but will delay the enabling of
its buffers until the next clock edge, avoiding bus contention.
When the data transfer is no longer required by the ISP1508, it changes DIR from HIGH to
LOW and starts to immediately turn off its output drivers. The link senses the change of
DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle,
avoiding data bus contention.
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The ISP1508 drives DIR to LOW.
The data bus is input to the ISP1508.
The ULPI link data bus is output, with all data bus lines driven to LOW.
Rev. 02 — 13 March 2008
ISP1508A; ISP1508B
ULPI HS USB OTG transceiver
© NXP B.V. 2008. All rights reserved.
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