ISP1508BET STEricsson, ISP1508BET Datasheet - Page 22

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 9.
ISP1508A_ISP1508B_2
Product data sheet
Signal name
CLOCK
DATA[7:0]
ULPI signal description
9.2.1 Synchronous mode
Direction on
the ISP1508
O
I/O
9.2 ULPI modes
using pull-up or pull-down resistors to avoid floating input condition. Other pins (see
Section
detect the CHIP_SEL pin status.
The ISP1508 ULPI interface can be programmed to operate in five modes. In each mode,
the signals on the data bus are reconfigured as described in the following subsections.
Setting more than one mode will lead to undefined behavior.
This is default mode. On power-up and when CLOCK is stable, the ISP1508 will enter
synchronous mode.
In synchronous mode, the link must synchronize all ULPI signals to CLOCK, meeting the
set-up time and the hold time as defined in
This mode is used by the link to perform the following tasks:
For more information on various synchronous mode protocols, see
•
•
•
•
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RXCMDs) from the ISP1508
Signal description
60 MHz interface clock: When a crystal is attached or a clock is driven into the XTAL1 pin,
the ISP1508 will drive a 60 MHz output clock.
During low-power, serial and UART modes, the clock is turned off to save power.
8-bit data bus: In synchronous mode, the link drives DATA[7:0] to LOW by default. The link
initiates transfers by sending a nonzero data pattern called a TXCMD (transmit command).
In synchronous mode, the direction of DATA[7:0] is controlled by DIR. Contents of
DATA[7:0] lines must be ignored for exactly one clock cycle whenever DIR changes value.
This is called a turnaround cycle.
Data lines have fixed directions and different meanings in low-power, 3-pin serial and UART
modes.
7.10) are not powered. In this mode, minimum current will be drawn by V
Rev. 02 — 13 March 2008
Section
ISP1508A; ISP1508B
15.
ULPI HS USB OTG transceiver
Section
© NXP B.V. 2008. All rights reserved.
10.
CC(I/O)
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