ISP1508BET STEricsson, ISP1508BET Datasheet - Page 18

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1508A_ISP1508B_2
Product data sheet
8.11 Power-up, reset and bus idle sequence
Figure 6
On power-up, the ISP1508 performs an internal power-on reset and asserts DIR to
indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the
ISP1508 de-asserts DIR and drives 60 MHz clock out from the CLOCK pin. The power-up
time depends on the V
t
default, the link must drive data to LOW. Before beginning USB packets, the link must set
the RESET bit in the Function Control register to reset the ISP1508. After the RESET bit
is set, the ISP1508 will assert DIR until the internal reset completes. The ISP1508 will
automatically de-assert DIR and clear the RESET bit when the reset has completed. After
every reset, an RXCMD is sent to the link to update USB status information. After this
sequence, the ULPI bus is ready for use and the link can start USB operations.
If V
power-down mode. In power-down mode, all ULPI interface pins will be put in 3-state, the
internal regulator will be shut down (see
be less than I
The link can do a hardware reset to the ISP1508 by toggling the CHIP_SEL pin. The
recommended sequence is:
The recommended power-up sequence for the link is:
The ULPI interface is ready for use.
startup(PLL)
1. De-activate the CHIP_SEL pin.
2. Wait for at least t
3. Activate the CHIP_SEL pin.
1. Apply the V
2. Activate the CHIP_SEL pin.
3. The link waits for at least t
4. The link may start to detect the DIR status level. If DIR is detected LOW, the link may
Fig 5.
CC(I/O)
send a RESET command.
shows a typical start-up sequence.
Internal power-on reset timing
is not present or the CHIP_SEL pin is non-active, the ISP1508 will be kept in
. When DIR is de-asserted, the link must drive the data bus to a valid level. By
t0
CC
CC
in power-down mode.
t1
and V
PWRDN
CC
Rev. 02 — 13 March 2008
CC(I/O)
supply rise time, the crystal start-up time, and PLL start-up time
.
PWRUP
power.
, ignoring all the ULPI pin status.
t2
Table
ISP1508A; ISP1508B
t3
8), and the total power current from V
t4
ULPI HS USB OTG transceiver
t5
© NXP B.V. 2008. All rights reserved.
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REG1V8
V
POR
POR(trip)
17 of 86
CC
will