ISP1508BET STEricsson, ISP1508BET Datasheet - Page 59

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 46.
Table 47.
Table 48.
Table 49.
ISP1508A_ISP1508B_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 4
3
2
1 to 0
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1 to 0
Symbol
-
DP_WKPU_EN DP Weak Pull-Up Enable: Enable the weak pull-up resistor on the DP pin (R
BVALID_FALL
BVALID_RISE
-
Carkit Control register (address R = 19h to 1Bh, W = 19h, S = 1Ah, C = 1Bh) bit allocation
Carkit Control register (address R = 19h to 1Bh, W = 19h, S = 1Ah, C = 1Bh) bit description
Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description
Symbol
-
RXD_EN
TXD_EN
-
11.12 Power Control register
R/W/S/C
R/W/S/C
7
0
7
0
For bit allocation, see
This vendor-specific register controls the power feature of the ISP1508. The bit allocation
of the register is given in
Description
reserved; the link must never write logic 1 to these bits
RXD Enable: Routes the UART RXD signal from the DP pin to the DATA1 pin. This bit will
automatically be cleared when UART mode is exited.
TXD Enable: Routes the UART TXD signal from the DATA0 pin to the DM pin. This bit will
automatically be cleared when UART mode is exited.
reserved; the link must never write logic 1 to these bits
Description
reserved; the link must never write logic 1 to these bits
synchronous mode when V
is in UART mode, the DP weak pull-up will be enabled, regardless of the value of this register bit.
0 — DP weak pull-up is disabled.
1 — DP weak pull-up is enabled when V
BValid Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID changes
from HIGH to LOW, the ISP1508 will send an RXCMD to the link with the ALT_INT bit set to
logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. Disabled by default.
BValid Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID changes
from LOW to HIGH, the ISP1508 will send an RXCMD to the link with the ALT_INT bit set to
logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. Disabled by default.
reserved; the link must never write logic 1 to these bits
R/W/S/C
reserved
R/W/S/C
6
0
6
0
reserved
R/W/S/C
R/W/S/C
5
0
5
0
Table
Rev. 02 — 13 March 2008
Table
BUS
46.
DP_WKPU
R/W/S/C
R/W/S/C
is above the V
48.
_EN
4
0
4
0
BUS
RXD_EN
BVALID_
> V
R/W/S/C
R/W/S/C
A_SESS_VLD
FALL
A_SESS_VLD
3
0
3
0
ISP1508A; ISP1508B
threshold. Note that when the ISP1508
BVALID_
TXD_EN
R/W/S/C
R/W/S/C
.
RISE
ULPI HS USB OTG transceiver
2
0
2
0
R/W/S/C
R/W/S/C
1
0
1
0
© NXP B.V. 2008. All rights reserved.
weakUP(DP)
reserved
reserved
R/W/S/C
R/W/S/C
) in
0
0
0
0
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