ISP1508BET STEricsson, ISP1508BET Datasheet - Page 42

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ISP1508BET

Manufacturer Part Number
ISP1508BET
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1508BET

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ISP1508BETTM
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NXP Semiconductors
ISP1508A_ISP1508B_2
Product data sheet
Fig 18. Full-speed suspend and resume
Timing is not to scale.
SUSPEND
OPMODE
OPMODE
CLOCK
STATE
STATE
DATA
DATA
10.7.2 High-speed suspend and resume
LINE
LINE
NXT
NXT
[ 7:0 ]
STP
[ 7:0 ]
STP
DIR
DIR
DM
DP
M
Figure 19
suspend and then initiates resume signaling. The high-speed peripheral will wake up and
return to high-speed operations. Note that
show all RXCMD LINESTATE updates.
idle
00b
(REGW)
TXCMD
J
J
illustrates how a host or a hub places a high-speed enabled peripheral into
00b
LINESTATE J
suspend
(REGW)
TXCMD
Rev. 02 — 13 March 2008
TXCMD
NOPID
LINESTATE K
resume K
K
K
10b
Figure 19
K
K
ISP1508A; ISP1508B
...
10b
K
timing is not to scale, and does not
SE0
SE0
SE0
EOP
ULPI HS USB OTG transceiver
J
TXCMD
J
© NXP B.V. 2008. All rights reserved.
00b
J
00b
idle
004aaa715
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