PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 65

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

4.2.5
The Extended Data Space (EDS) allows PIC24F
devices to address a much larger range of data than
would otherwise be possible with a 16-bit address
range. EDS includes any additional internal data mem-
ory not directly accessible by the lower 32-Kbyte data
address space, and any external memory through
EPMP.
In addition, EDS also allows read access to the
program memory space. This feature is called Program
Space Visibility (PSV), and is discussed in detail in
Section 4.3.3 “Reading Data from Program Memory
Using
Figure 4-4
organized as pages, called EDS pages, with one page
equal to size of the EDS window (32 Kbytes). A partic-
ular EDS page is selected through the Data Space
Read register (DSRPAG) or Data Space Write register
(DSWPAG). For PSV, only the DSRPAG register is
used. The combination of the DSRPAG register value
and the 16-bit wide data address forms a 24-bit
Effective Address (EA).
FIGURE 4-4:
 2010-2011 Microchip Technology Inc.
Note
EDS”.
1:
displays the entire EDS space. The EDS is
EXTENDED DATA SPACE (EDS)
30 Kbytes)
Registers
32-Kbyte
Function
Memory
Special
Window
Internal
Space
(up to
Data
EDS
The range of addressable memory available is dependent on the device pin count and EPMP implementation.
0800h
8000h
0000h
FFFEh
EXTENDED DATA SPACE
External
Access
EPMP
00FFFEh
DSxPAG
= 001h
008000h
Memory
using
EPMP Memory Space
(1)
PIC24FJ128GA310 FAMILY
FFFFFEh
DSx PAG
= 1FFh
FF8000h
EPMP
External
Memory
Access
using
(1)
(1)
DSRPAG
= 200h
007FFEh
000000h
Program
Access
(Lower
Space
Word)
The data addressing range of PIC24FJ128GA310 family
devices depends on the version of the Enhanced
Parallel Master Port implemented on a particular device;
this is in turn a function of device pin count.
lists the total memory accessible by each of the devices
in this family. For more details on accessing external
memory using EPMP, refer to the “PIC24F Family Refer-
ence Manual”,
Port (EPMP)”
.
TABLE 4-35:
PIC24FJXXXGA310
PIC24FJXXXGA308
PIC24FJXXXGA306
Note:
EDS Pages
Family
Accessing Page 0 in the EDS window will
generate an address error trap as Page 0
is the base data memory (data locations
0800h to 7FFFh in the lower data space).
7FFFFEh
DSRPAG
= 2FFh
7F8000h
Program
Access
(Lower
Space
Word)
Section 42. “Enhanced Parallel Master
(DS39730).
Program Memory
TOTAL ACCESSIBLE DATA
MEMORY
Internal
DSRPAG
= 300h
007FFFh
000001h
Program
Access
(Upper
Space
Word)
RAM
8K
8K
8K
DS39996F-page 65
Up to 16 MB
Up to 64K
Up to 64K
Access Using
External RAM
7FFFFFh
DSRPAG
= 3FFh
7F8001h
Program
Access
(Upper
Space
Word)
EPMP
Table 4-35