PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 305

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

REGISTER 24-5:
 2010-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-10
bit 9-8
bit 7-4
bit 3-2
bit 1-0
R/W-0
ASEN
U-0
—
ASEN: Auto-Scan Enable bit
1 = Auto-scan is enabled
0 = Auto-scan is disabled
LPEN: Low-Power Enable bit
1 = Low power is enabled after scan
0 = Full power is enabled after scan
CTMREQ: CTMU Request bit
1 = CTMU is enabled when the A/D is enabled and active
0 = CTMU is not enabled by the A/D
BGREQ: Band Gap Request bit
1 = Band gap is enabled when the A/D is enabled and active
0 = Band gap is not enabled by the A/D
Unimplemented: Read as ‘0’
ASINT<1:0>: Auto-Scan (Threshold Detect) Interrupt Mode bits
11 = Interrupt after Threshold Detect sequence completed and valid compare has occurred
10 = Interrupt after valid compare has occurred
01 = Interrupt after Threshold Detect sequence completed
00 = No interrupt
Unimplemented: Read as ‘0’
WM<1:0>: Write Mode bits
11 = Reserved
10 = Auto-compare only (conversion results are not saved, but interrupts are generated when a valid
01 = Convert and save (conversion results are saved to locations as determined by the register bits
00 = Legacy operation (conversion data is saved to a location determined by the buffer register bits)
CM<1:0>: Compare Mode bits
11 = Outside Window mode (valid match occurs if the conversion result is outside of the window defined by
10 = Inside Window mode (valid match occurs if the conversion result is inside the window defined by the
01 = Greater Than mode (valid match occurs if the result is greater than the value in the corresponding
00 = Less Than mode (valid match occurs if the result is less than the value in the corresponding buffer
R/W-0
LPEN
U-0
match occurs, as defined by the CM and ASINT bits)
when a match occurs, as defined by the CM bits)
the corresponding buffer pair)
corresponding buffer pair)
buffer register)
register)
—
AD1CON5: A/D CONTROL REGISTER 5
W = Writable bit
‘1’ = Bit is set
CTMREQ
R/W-0
U-0
—
PIC24FJ128GA310 FAMILY
BGREQ
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
WM1
U-0
—
R/W-0
WM0
U-0
—
x = Bit is unknown
ASINT1
R/W-0
R/W-0
CM1
DS39996F-page 305
ASINT0
R/W-0
R/W-0
CM0
bit 8
bit 0