PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 290

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

polynomials of up to the 32
PIC24FJ128GA310 FAMILY
23.1
23.1.1
The CRC module can be programmed for CRC
Polynomial length, which reflects the highest exponent
in the equation, is selected by the PLEN<4:0> bits
(CRCCON2<4:0>).
The CRCXORL and CRCXORH registers control which
exponent terms are included in the equation. Setting a
particular bit includes that exponent term in the equa-
tion. Functionally, this includes an XOR operation on
the corresponding bit in the CRC engine. Clearing the
bit disables the XOR.
For example, consider two CRC polynomials, one a
16-bit and the other a 32-bit equation.
EQUATION 23-1:
To program these polynomial into the CRC generator,
set the register bits, as shown in
Note that the appropriate positions are set to ‘1’ to indi-
cate that they are used in the equation (for example,
X26 and X23). The ‘0’ bit required by the equation is
always XORed; thus, X0 is a don’t care. For a poly-
nomial of length 32, it is assumed that the 32
be used. Therefore, the X<31:1> bits do not have the
32
TABLE 23-1:
DS39996F-page 290
nd
X32+X26 + X23 + X22 + X16 + X12 + X11 + X10 +
bit.
CRC Control Bits
User Interface
X8 + X7 + X5 + X4 + X2 + X + 1
POLYNOMIAL INTERFACE
PLEN<4:0>
X<31:16>
X<15:0>
X16 + X12 + X5 + 1
CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS
16-BIT, 32-BIT CRC
POLYNOMIALS
and
nd
order, using up to 32 bits.
Table
23-1.
0000 0000 0000 0001
0001 0000 0010 000X
nd
16-Bit Polynomial
bit will
01111
23.1.2
The module incorporates a FIFO that works with a
variable data width. Input data width can be configured
to any value between 1 and 32 bits using the
DWIDTH<4:0> bits (CRCCON2<12:8>). When the
data width is greater than 15, the FIFO is 4 words deep.
When the DWITDH bits are between 15 and 8, the
FIFO is 8 words deep. When the DWIDTH bits are less
than 8, the FIFO is 16 words deep.
The data for which the CRC is to be calculated must
first be written into the FIFO. Even if the data width is
less than 8, the smallest data element that can be writ-
ten into the FIFO is 1 byte. For example, if the DWIDTH
bits
DWIDTH<4:0> + 1 or 6. The data is written as a whole
byte; the two unused upper bits are ignored by the
module.
Once data is written into the MSb of the CRCDAT reg-
isters (that is, the MSb as defined by the data width),
the value of the VWORD<4:0> bits (CRCCON1<12:8>)
increments by one. For example, if the DWIDTH bits
are 24, the VWORD bits will increment when bit 7 of
CRCDATH is written. Therefore, CRCDATL must
always be written to before CRCDATH.
The CRC engine starts shifting data when the CRCGO
bit is set and the value of the VWORD bits is greater
than zero.
Each word is copied out of the FIFO into a buffer regis-
ter, which decrements the VWORD bits. The data is
then shifted out of the buffer. The CRC engine contin-
ues shifting at a rate of two bits per instruction cycle,
until the VWORD bits reach zero. This means that for a
given data width, it takes half that number of instruc-
tions for each word to complete the calculation. For
example, it takes 16 cycles to calculate the CRC for a
single word of 32-bit data.
When the VWORD bits reach the maximum value for
the configured value of the DWIDTH bits (4, 8 or 16),
the CRCFUL bit becomes set. When the VWORD bits
reach zero, the CRCMPT bit becomes set. The FIFO is
emptied and the VWORD<4:0> bits are set to ‘00000’
whenever CRCEN is ‘0’.
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORD bits is done.
are
Bit Values
DATA INTERFACE
5,
then
 2010-2011 Microchip Technology Inc.
0000 0100 1100 0001
0001 1101 1011 011x
the
32-Bit Polynomial
size
11111
of
the
data
is