PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 253

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

20.0
The Enhanced Parallel Master Port (EPMP) module
provides a parallel, 4-bit (Master mode only), 8-bit
(Master and Slave modes) or 16-bit (Master mode only)
data bus interface to communicate with off-chip mod-
ules, such as memories, FIFOs, LCD controllers and
other microcontrollers. This module can serve as either
the master or the slave on the communication bus.
For EPMP Master modes, all external addresses are
mapped into the internal Extended Data Space (EDS).
This is done by allocating a region of the EDS for each
chip select, and then assigning each chip select to a
particular external resource, such as a memory or
external controller. This region should not be assigned
to another device resource, such as RAM or SFRs. To
perform a write or read on an external resource, the
CPU simply performs a write or read within the address
range assigned for the EPMP.
Key features of the EPMP module are:
• Extended Data Space (EDS) interface allows
• Up to 23 Programmable Address Lines
• Up to 2 Chip Select lines
• Up to 2 Acknowledgement Lines
• 4-bit, 8-bit or 16-bit wide Data Bus
• Programmable Strobe Options (per chip select)
• Programmable Address/Data Multiplexing
TABLE 20-1:
 2010-2011 Microchip Technology Inc.
PIC24FJXXXGA306 (64-pin)
PIC24FJXXXGA308 (80-pin)
PIC24FJXXXGA310 (100-pin)
Note:
direct access from the CPU
(one per chip select)
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
ENHANCED PARALLEL
MASTER PORT (EPMP)
Section 42. “Enhanced Parallel Master
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
Port (EPMP)” (DS39730). The informa-
tion in this data sheet supersedes the
information in the FRM.
Device
EPMP FEATURE DIFFERENCES BY DEVICE PIN COUNT
Family
Reference
Dedicated Chip Select
CS1
—
X
X
Manual”,
PIC24FJ128GA310 FAMILY
CS2
—
—
X
• Programmable Address Wait States
• Programmable Data Wait States (per chip select)
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
20.1
While all PIC24FJ128GA310 family devices implement
the EPMP, I/O pin constraints place some limits on
16-Bit Master mode operations in some package types.
This is reflected in the number of dedicated Chip Select
pins implemented and the number of dedicated
address lines that are available. The differences are
summarized in
functions are summarized in
For 64-pin devices, the dedicated Chip Select pins
(PMCS1 and PMCS2) are not implemented. In addi-
tion, only 16 address lines (PMA<15:0>) are available.
If required, PMA14 and PMA15 can be remapped to
function as PMCS1 and PMCS2, respectively.
For 80-pin devices, the dedicated PMCS2 pin is not
implemented. It also only implements 16 address lines
(PMA<15:0>). If required, PMA15 can be remapped to
function as PMCS2.
The memory space addressable by the device
depends on the number of address lines available, as
well as the number of Chip Select signals required for
the application. Devices with lower pin counts are more
affected by Chip Select requirements, as these take
away address lines.
addressable range for each pin count.
Address
(per chip select)
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
Lines
16
16
23
Specific Package Variations
No CS
Table
64K
Address Range (bytes)
Table 20-1
20-1. All available EPMP pin
64K
Table
1 CS
16M
32K
shows the maximum
20-2.
DS39996F-page 253
2 CS
16K
32K