PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 157

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

10.1.2
The hardware-based V
action by the user during code development. Instead, it
is a hardware design feature that allows the micro-
controller to retain critical data (using the DSGPRn
registers) and maintain the RTCC when V
from the application. This is accomplished by supplying
a backup power source to a specific power pin. V
mode is described in more detail in
Mode”.
10.1.3
PIC24FJ128GA310 family devices incorporate a
second on-chip voltage regulator, designed to provide
power to select microcontroller features at 1.2V nomi-
nal. This regulator allows features, such as data RAM
and the WDT, to be maintained in power-saving modes
where they would otherwise be inactive, or maintain
them at a lower power than would otherwise be the
case.
The low-voltage/retention regulator is only available
when Sleep or Deep Sleep modes are invoked. It is
controlled by the LPCFG Configuration bit (CW1<10>)
and in firmware by the RETEN bit (RCON<12>).
LPCFG must be programmed (= 0) and the RETEN bit
must be set (= 1) for the regulator to be enabled.
10.2
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
• If the WDT or FSCM is enabled, the LPRC will
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction or the first instruction in the ISR.
 2010-2011 Microchip Technology Inc.
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see
“Selective Peripheral Module
also remain active.
Idle Mode
HARDWARE-BASED
POWER-SAVING MODE
LOW-VOLTAGE/RETENTION
REGULATOR
BAT
mode does not require any
Control”).
Section 10.5 “Vbat
Section 10.8
DD
is removed
PIC24FJ128GA310 FAMILY
BAT
10.3
Sleep mode includes these features:
• The system clock source is shut down. If an
• The device current consumption will be reduced
• The I/O pin directions and states are frozen.
• The Fail-Safe Clock Monitor does not operate
• The LPRC clock will continue to run in Sleep
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may
The device will wake-up from Sleep mode on any of
these events:
• On any interrupt source that is individually
• On any form of device Reset
• On a WDT time-out
On wake-up from Sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
10.3.1
Low-Voltage/Retention Sleep mode functions as Sleep
mode with the same features and wake-up triggers.
The difference is that the low-voltage/retention regula-
tor allows core digital logic voltage (V
1.2V nominal. This permits an incremental reduction of
power consumption over what would be required if
V
Low-Voltage Sleep mode requires a longer wake-up
time than Sleep mode, due to the additional time
required to bring V
In addition, the use of the low-voltage/retention regula-
tor limits the amount of current that can be sourced to
any active peripherals, such as the RTCC/LCD, etc.
CORE
on-chip oscillator is used, it is turned off.
to a minimum provided that no I/O pin is sourcing
current.
during Sleep mode since the system clock source
is disabled.
mode if the WDT or RTCC, with LPRC as clock
source, is enabled.
prior to entering Sleep mode.
continue to operate in Sleep mode. This includes
items, such as the input change notification on the
I/O ports, or peripherals that use an external clock
input. Any peripheral that requires the system
clock source for its operation will be disabled in
Sleep mode.
enabled
was maintained at a 1.8V (minimum) level.
Sleep Mode
LOW-VOLTAGE/RETENTION SLEEP
MODE
CORE
back to 1.8V (known as T
DS39996F-page 157
CORE
) to drop to
REG
).