PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 396

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

PIC24FJ128GA310 FAMILY
D
Data Memory
Data Signal Modulator....................................................... 249
Data Signal Modulator (DSM) ........................................... 249
DC Characteristics
Development Support ....................................................... 347
Device Features
Direct Memory Access Controller. See DMA.
DMA .................................................................................... 75
DMA Controller.................................................................... 12
E
Electrical Characteristics
Enhanced Parallel Master Port (EPMP)............................ 253
Enhanced Parallel Master Port. See EPMP...................... 253
EPMP
DS39996F-page 396
Address Space............................................................ 43
Extended Data Space (EDS) ...................................... 65
Memory Map ............................................................... 43
Near Data Space ........................................................ 44
SFR Space.................................................................. 44
Software Stack ............................................................ 68
Space Organization, Alignment .................................. 44
Comparator ............................................................... 368
Comparator Voltage Reference ................................ 368
CTMU Current Source .............................................. 367
I/O Pin Input Specifications ....................................... 365
I/O Pin Output Specifications .................................... 366
Idle Current ............................................................... 362
Operating Current ..................................................... 361
Power-Down Current ................................................ 363
Program Memory ...................................................... 366
Resets ....................................................................... 364
Temperature and Voltage Specifications .................. 361
Vbat Operating Voltage Specifications ..................... 367
100-Pin........................................................................ 15
64-Pin.......................................................................... 13
80-Pin.......................................................................... 14
Channel Trigger Sources ............................................ 82
Peripheral Module Disable (PMD) .............................. 78
Summary of Operations .............................................. 76
Types of Transfers ...................................................... 77
Typical Setup .............................................................. 78
Absolute Maximum Ratings ...................................... 359
Capacitive Loading on Output Pin ............................ 369
CLKO and I/O Timing................................................ 372
External Clock Timing ............................................... 370
High/Low-Voltage Detect .......................................... 368
Internal Voltage Regulator Specifications ................. 367
PLL Clock Timing Specifications............................... 371
RC Oscillator Start-up Time ...................................... 371
Reset and Brown-out Reset Requirements .............. 373
Thermal Conditions ................................................... 360
V/F Graph ................................................................. 360
Key Features............................................................. 253
Package Variations ................................................... 253
Equations
Errata .................................................................................. 10
Extended Data Space (EDS) ............................................ 253
F
Flash Configuration Word Locations................................. 333
Flash Configuration Words ................................................. 42
Flash Program Memory ...................................................... 83
H
High/Low-Voltage Detect (HLVD) ..................................... 331
I
I/O Ports
I
Input Capture
Input Capture with Dedicated Timers ............................... 205
Input Voltage Levels for Port or Pin Tolerated
Instruction Set
Interfacing Program and Data Spaces................................ 69
Inter-Integrated Circuit. See I
Internet Address ............................................................... 400
Interrupt Vector Table (IVT) ................................................ 95
2
C
16-Bit, 32-Bit CRC Polynomials................................ 290
A/D Conversion Clock Period ................................... 311
Baud Rate Reload Calculation.................................. 235
Calculating the PWM Period..................................... 214
Calculation for Maximum PWM Resolution .............. 215
Relationship Between Device and
UART Baud Rate with BRGH = 0 ............................. 242
UART Baud Rate with BRGH = 1 ............................. 242
and Table Instructions ................................................ 83
Enhanced ICSP Operation ......................................... 84
JTAG Operation.......................................................... 84
Programming Algorithm .............................................. 86
Programming Operations............................................ 84
RTSP Operation ......................................................... 84
Single-Word Programming ......................................... 88
Analog Port Pins Configuration (ANSx) .................... 168
Analog/Digital Function of an I/O Pin........................ 168
Input Change Notification ......................................... 172
Open-Drain Configuration......................................... 168
Parallel (PIO) ............................................................ 167
Peripheral Pin Select ................................................ 173
Pull-ups and Pull-Downs........................................... 172
Selectable Input Sources.......................................... 174
Clock Rates .............................................................. 235
Communicating as Master in Single
Reserved Addresses ................................................ 235
Setting Baud Rate as Bus Master............................. 235
Slave Address Masking ............................................ 235
32-Bit Cascaded Mode ............................................. 206
Operations ................................................................ 206
Synchronous and Trigger Modes.............................. 205
Description Input....................................................... 168
Overview................................................................... 353
Summary .................................................................. 351
Symbols Used in Opcode Descriptions .................... 352
SPI Clock Speed .............................................. 231
Master Environment ......................................... 233
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C. ...................................... 233