PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 163

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

REGISTER 10-2:
 2010-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 8
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
R/W-0, HS
DSFLT
U-0
—
All register bits are cleared when the DSEN (DSCON<15>) bit is set.
Unimplemented: Read as ‘0’
DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
DSFLT: Deep Sleep Fault Detected bit
1 = A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been
0 = No Fault was detected during Deep Sleep
Unimplemented: Read as ‘0’
DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
DSRTCC: Real-Time Clock and Calendar Alarm bit
1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
DSMCLR: MCLR Event bit
1 = The MCLR pin was active and was asserted during Deep Sleep
0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep
Unimplemented: Read as ‘0’
corrupted
U-0
U-0
—
—
DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER
HS = Hardware Settable bit
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
R/W-0, HS
PIC24FJ128GA310 FAMILY
DSWDT
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0, HS
DSRTCC
U-0
—
R/W-0, HS
DSMCLR
U-0
—
(1)
x = Bit is unknown
U-0
U-0
—
—
DS39996F-page 163
R/W-0, HS
DSINT0
U-0
—
bit 8
bit 0