DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 54

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
54
Bit #
Example 1. Boundary Scan Register – BSR (Sheet 2 of 3)
MOT/INTL
RPOS1
RNEG1
LOOP0
LOOP0
LOOP1
LOOP1
LOOP2
LOOP2
LOOP3
LOOP3
LOOP4
LOOP4
LOOP5
LOOP5
LOOP6
LOOP6
LOOP7
LOOP7
RESET
TPOS1
TNEG1
RCLK1
TCLK1
Signal
LOS1
MUX
R/W
N/A
N/A
Pin
A2
A3
A4
CS
DS
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
-
-
I
I
I
I
I
I
I
I
I
I
I
I
PDOENB
Symbol
RNEG1
PADD0
TPOS1
TNEG1
RPOS1
RCLK1
TCLK1
PDO0
PADI1
PDO1
PADI2
PDO2
PADI3
PDO3
PADI4
PDO4
PADI5
PDO5
PADI6
PDO6
PADI7
PDO7
RSTB
LOS1
WRB
MUX
HIZ1
CSB
RDB
IMB
Bit
A2
A3
A4
PDOENB controls the LOOP0 through LOOP7 pins.
Setting PDOENB to “0” configures the pins as outputs. The output value
to the pin is set in PDO[0..7].
Setting PDOENB to “1” tristates all the pins. The input value to the pins
can be read in PADD[0..7].
HIZ1 controls the RPOS1, RNEG1 and RCLK1 pins. Setting HIZ1 to “0”
enables output on the pins. Setting HIZ1 to “1” tristates the pins.
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