DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 37

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

3.8
3.9
Datasheet
G.772 Performance Monitoring
The LXT386 can be configured as a quad line interface unit with all channels working as regular
transceivers. In applications using only three channels, the fourth channel can be configured to
monitor any of the remaining channels inputs or outputs. The monitoring is non-intrusive per ITU-
T G.772.
The monitored line signal (input or output) goes through channel 0 clock and data recovery. The
signal can be observed digitally at the RCLK/RPOS/RNEG outputs. This feature can also be used
to create timing interfaces derived from an E1 or T1 signal.
In addition, channel 0 can be configured to a Remote Loopback while in monitoring mode (TCLK0
must be active in order for this operation to take place). This will output the same data as in the
signal being monitored at the channel 0 output (TTIP/TRING). The output signal can then be
connected to a standard test equipment with a T1/E1 electrical interface for monitoring purposes
(non-intrusive monitoring).
Hitless Protection Switching (HPS)
The LXT386 transceivers include an output driver tristatability feature for T1/E1 redundancy
applications. This feature greatly reduces the cost of implementing redundancy protection by
eliminating external relays. Please refer to Application Note 119 for guidelines for implementing
redundancy systems for both T1 and E1 operation using the LXT380/1/4/6.
Figure 2 on page 8
illustrates this concept.
QUAD T1/E1/J1 Transceiver — LXT386
37