DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 32

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
3.6
32
Table 3.
Jitter Attenuation
A digital Jitter Attenuation Loop (JAL) combined with a FIFO provides Jitter attenuation. The JAL
is internal and requires no external crystal nor high-frequency (higher than line rate) reference
clock.
In Host Mode, the Global Control Register (GCR) determines whether the JAL is positioned in the
receive or transmit path. In Hardware Mode, the JAL position is determined by the JASEL pin.
The FIFO is a 32 x 2-bit or 64 x 2-bit register (selected by the FIFO64 bit in the GCR). Data is
clocked into the FIFO with the associated clock signal (TCLK or RCLK), and clocked out of the
FIFO with the dejittered JAL clock. See
or underflowing, the FIFO adjusts the output clock by
produces a constant delay of 17 or 33 bits in the associated path (refer to test specifications). This
feature can be used for hitless switching applications. This advanced digital jitter attenuator meets
latest jitter attenuation specifications. See
Under software control, the low limit jitter attenuator corner frequency depends on FIFO length
and the JACF bit setting (this bit is in the GCR register). In Hardware Mode, the FIFO length is
fixed to 64 bits. The corner frequency is fixed to 6 Hz for T1 mode and 3.5 Hz for E1 mode.
Jitter Attenuation Specifications
1. Category I, R5-203.
2. Section 4.6.3.
3. Section 6.2 When used with the SXT6234 E2-E1 mux/demux.
4. Section 6.2.3.3 combined jitter when used with the SXT6251 21E1 mapper.
AT&T Pub 62411
TR-TSY-000009
GR-253-CORE
T1
1
2
Figure
Table
8. When the FIFO is within two bits of overflowing
3.
1/8
of a bit period. The Jitter Attenuator
ETSI CTR12/13
ITU-T G.742
ITU-T G.783
ITU-T G.736
BAPT 220
E1
3
4
Datasheet