DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 11

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
2. N/C means “Not Connected”
PBGA
Ball #
N.C.: Not Connected.
Table 1. Pin Assignments and Signal Descriptions (Sheet 1 of 11)
E1
E2
F4
LQFP
Pin #
78
79
89
Symbol
MODE
MCLK
A4
I/O
DI
DI
DI
1
Master Clock. MCLK is an independent, free-running reference clock. It’s
frequency should be 1.544 MHz for T1 operation and 2.048 MHz for E1
operation.
This reference clock is used to generate several internal reference
signals:
If MCLK is High, the PLL clock recovery circuit is disabled. In this mode,
the LXT386 operates as simple data receiver.
If MCLK is Low, the complete receive path is powered down and the
output pins RCLK, RPOS and RNEG are switched to Tri-state mode.
MCLK is not required if LXT386 is used as a simple analog front-end
without clock recovery and jitter attenuation.
Note that wait state generation via RDY/ACK is not available if MCLK is
not provided.
Mode Select. This pin is used to select the operating mode of the
LXT386. In Hardware Mode, the parallel processor interface is disabled
and hardwired pins are used to control configuration and report status.
In Parallel Host Mode, the parallel port interface pins are used to control
configuration and report status.
In Serial Host Mode the serial interface pins: SDI, SDO, SCLK and CS are
used.
For Serial Host Mode, the pin should connected to a resistive divider
consisting of two 10 kΩ resistors across V
Address Select. In host mode, this pin is Address 4 input pin. In hardware
mode this pin must be connected to Ground.
• Timing reference for the integrated clock recovery unit
• Timing reference for the integrated digital jitter attenuator
• Generation of RCLK signal during a loss of signal condition
• Reference clock during a blue alarm transmit all ones condition
• Reference timing for the parallel processor wait state generation logic
MODE
Vcc/2
H
L
QUAD T1/E1/J1 Transceiver — LXT386
Parallel Host Mode
Serial Host Mode
Operating Mode
Hardware Mode
Description
CC
and Ground.
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