DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 50

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
5.0
5.1
5.2
50
Figure 15. LXT386 JTAG Architecture
JTAG Boundary Scan
Overview
The LXT386 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy
access to the interface pins for board testing purposes.
In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT386 also
includes analog test port capabilities. This feature provides access to the TIP and RING signals in
each channel (transmit and receive). This way, the signal path integrity across the primary winding
of each coupling transformer can be tested.
Architecture
Figure 15
includes a TAP Test Access Port Controller, data registers and an instruction register. The
following paragraphs describe these blocks in detail.
represents the LXT386 basic JTAG architecture. The LXT386 JTAG architecture
TRST
TMS
TCK
TDI
Controller
TAP
Device Identification Register
Boundry Scan Data Register
Analog Port Scan Register
Instruction Register
Bypass Register
BSR
ASR
BYR
IDR
IR
MUX
Datasheet
TDO