DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 17

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
2. N/C means “Not Connected”
PBGA
Ball #
N.C.: Not Connected.
Table 1. Pin Assignments and Signal Descriptions (Sheet 7 of 11)
M12
M13
M14
N12
N13
N14
K12
K13
K14
L12
L13
L14
LQFP
Pin #
55
56
57
58
59
60
61
62
63
64
80
81
RDATA2
Symbol
TNEG3/
TDATA3
RNEG2/
RPOS2/
TNEG2/
TDATA2
TPOS3/
TPOS2/
RCLK2
TCLK3
TCLK2
UBS3
LOS2
BPV2
UBS2
ACK/
RDY/
SDO
INT
I/O
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
1
Transmit Negative Data.
Unipolar/Bipolar Select.
Transmit Positive Data.
Transmit Data.
Transmit Clock.
Loss of Signal.
Receive Negative Data.
Bipolar Violation Detect.
Receive Positive Data.
Receive Data.
Receive Clock.
Transmit Negative Data.
Unipolar/Bipolar Select.
Transmit Positive Data.
Transmit Data.
Transmit Clock.
Interrupt. This active Low, maskable, open drain output requires an
external 10k pull up resistor. If the corresponding interrupt enable bit is
enabled, INT goes Low to flag the host when the LXT386 changes state
(see details in the interrupt handling section). The microprocessor INT
input should be set to level triggering.
Data Transfer acknowledge (Motorola Mode).
Ready (Intel mode).
Serial Data Output (Serial Mode).
Motorola Mode
A Low signal during a databus read operation indicates that the
information is valid. A Low signal during a write operation acknowledges
that a data transfer into the addressed register has been accepted
(acknowledge signal).Wait states only occur if a write cycle immediately
follows a previous read or write cycle (e.g. read modify write).
Intel Mode
A High signal acknowledges that a register access operation has been
completed (Ready Signal). A Low signal on this pin signals that a data
transfer operation is in progress. The pin goes tristate after completion of a
bus cycle.
Serial Mode
If CLKE is High, SDO is valid on the rising edge of SCLK. If CLKE is Low,
SDO is valid on the falling edge of SCLK. This pin goes into high Z state
during a serial port write access.
QUAD T1/E1/J1 Transceiver — LXT386
Description
17