DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 44

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
44
LOS Status Monitor
DFM Status Monitor
LOS Interrupt Enable
DFM Interrupt Enable
LOS Interrupt Status
DFM Interrupt Status
Software Reset
Register
Performance
Monitoring
Digital Loopback
LOS/AIS Criteria Select
Automatic TAOS Select
Global Control Register
Pulse Shaping Indirect
Address Register
Pulse Shaping Data
Register
Output Enable Register
AIS Status Register
AIS Interrupt Enable
AIS Interrupt Status
7-0
3-0
Bit
Bit
Table 7.
Table 8.
Table 9.
Name
Register
Register Bit Names (Continued)
ID Register, ID (00H)
Analog Loopback Register, ALOOP (01H)
AL3-AL0
ID7-ID0
Name
Name
PSDAT
PSIAD
LACS
AISIE
AISIS
MON
Sym
DFM
GCR
OER
LOS
RES
ATS
DIE
DIS
AIS
LIE
LIS
DL
This register contains a unique revision code and is mask programmed.
For Revision A1, ID register = 00h
For Revision B1, ID register = 21h
For Revision B2, ID register = 22h
Setting a bit to “1” enables analog local loopback for transceivers 3- 0 respectively.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RW
R
R
R
R
R
R
reserve
reserve
reserve
reserve
7
d
d
d
d
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserve
reserve
reserve
RAISE
N
6
d
d
d
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserve
reserve
reserve
CDIS
5
d
d
d
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CODEN
reserve
reserve
reserve
Function
Function
4
d
d
d
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit
FIFO64
reserve
reserve
LACS3
AISIE3
AISIS3
DFM3
RES3
LOS3
ATS3
DIE3
DIS3
AIS3
LIE3
LIS3
OE3
DL3
A3
3
d
d
LENAD2
LACS2
AISIE2
AISIS2
DFM2
LOS2
RES2
ATS2
JACF
LEN2
DIE2
DIS2
AIS2
LIE2
LIS2
OE2
DL2
A2
2
LENAD1
JASEL1
LACS1
AISIE1
AISIS1
DFM1
RES1
LOS1
LEN1
ATS1
DIE1
DIS1
LIE1
LIS1
AIS1
OE1
DL1
A1
1
Datasheet
LENAD0
JASEL0
LACS0
AISIE0
AISIS0
DFM0
LOS0
RES0
ATS0
LEN0
DIE0
DIS0
AIS0
LIE0
LIS0
OE0
DL0
A0
0