DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 3

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DJLXT386LE.B2 S E001

Manufacturer Part Number
DJLXT386LE.B2 S E001
Description
Manufacturer
Intel
Datasheet

Specifications of DJLXT386LE.B2 S E001

Lead Free Status / RoHS Status
Not Compliant
Contents
1.0
2.0
3.0
4.0
5.0
Datasheet
Features
Pin Assignments and Signal Description
Functional Description
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
Register Descriptions
JTAG Boundary Scan
5.1
5.2
Initialization.......................................................................................................... 22
3.1.1
Receiver .............................................................................................................. 24
3.2.1
3.2.2
3.2.3
Transmitter .......................................................................................................... 27
3.3.1
3.3.2
Driver Failure Monitor ..........................................................................................30
Line Protection .................................................................................................... 30
Jitter Attenuation .................................................................................................32
Loopbacks ........................................................................................................... 34
3.7.1
3.7.2
3.7.3
3.7.4
G.772 Performance Monitoring ........................................................................... 37
Hitless Protection Switching (HPS) ..................................................................... 37
Operation Mode Summary .................................................................................. 38
Interfacing with 5V logic ...................................................................................... 38
Parallel Host Interface ......................................................................................... 39
3.12.1 Motorola Interface .................................................................................. 40
3.12.2 Intel Interface..........................................................................................40
Interrupt Handling................................................................................................ 41
3.13.1 Interrupt Enable ...................................................................................... 41
3.13.2 Interrupt Clear ........................................................................................ 41
Serial Host Mode .................................................................................................42
Overview ............................................................................................................. 50
Architecture ......................................................................................................... 50
......................................................................................................................... 7
Reset Operation .....................................................................................23
Loss of Signal Detector .......................................................................... 25
3.2.1.1 E1 Mode .................................................................................... 25
3.2.1.2 T1 Mode .................................................................................... 25
3.2.1.3 Data Recovery Mode................................................................. 25
Alarm Indication Signal (AIS) Detection ................................................. 26
3.2.2.1 E1 Mode .................................................................................... 26
3.2.2.2 T1 Mode .................................................................................... 26
In Service Code Violation Monitoring ..................................................... 26
Transmit Pulse Shaping .........................................................................28
3.3.1.1 Hardware Mode .........................................................................28
3.3.1.2 Host Mode ................................................................................. 28
Transmit Pulse Shaping .........................................................................29
3.3.2.1 Output Driver Power Supply ...................................................... 29
3.3.2.2 Power Sequencing .................................................................... 29
Analog Loopback.................................................................................... 34
Digital Loopback .....................................................................................34
Remote Loopback .................................................................................. 35
Transmit All Ones (TAOS)...................................................................... 36
............................................................................................. 43
............................................................................................. 50
........................................................................................... 22
QUAD T1/E1/J1 Transceiver — LXT386
........................................................ 9
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