DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 42

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
3.14
42
Figure 14. Serial Host Mode Timing
SCLK
SDI
R/W = 1: Read from the LXT386
R/W = 0: Write to the LXT386
CS
X = Don’t care
Serial Host Mode
The LXT386 operates in Serial Host Mode when the MODE pin is tied to VCC÷2.
the SIO data structure. The registers are accessible through a 16 bit word: an 8bit Command/
Address byte (bits R/W and A1-A7) and a subsequent 8bit data byte (bits D0-7). Bit R/W
determines whether a read or a write operation occurs. Bits A5-0 in the Command/Address byte
address specific registers (the address decoder ignores bits A7-6). The data byte depends on both
the value of bit R/W and the address of the register as set in the Command/Address byte.
R/W
A1
ADDRESS/COMMAND BYTE
SDO - REMAINS HIGH Z
A2
A3
A4
A5
A6
X
A7
X
D0
D1
SDO IS DRIVEN IF R/W = 1
D2
INPUT DATA BYTE
D3
D4
D5
D6
Figure 14
D7
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