DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 24

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
3.2
24
Receiver
The four receivers in the LXT386 are identical. The following paragraphs describe the operation of
one.
The twisted-pair input is received via a 1:2 step down transformer. Positive pulses are received at
RTIP, negative pulses at RRING. Recovered data is output at RPOS and RNEG in the bipolar mode
and at RDATA in the unipolar mode. The recovered clock is output at RCLK. RPOS/RNEG
validation relative to RCLK is pin selectable (CLKE).
The receive signal is processed through the peak detector and data slicers. The peak detector
samples the received signal and determines its maximum value. A percentage of the peak value is
provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. For DSX-1
applications (line length inputs LEN2-0 from 011 to 111) the threshold is set to 70% (typical) of the
peak value. This threshold is maintained above the specified level for up to 15 successive zeros
over the range of specified operating conditions. For E1 applications (LEN2-0 = 000), the
threshold is 50% (typical).
The receiver is capable of accurately recovering signals with up to 12 dB of attenuation (from 2.4
V), corresponding to a received signal level of approximately 500 mV. Maximum line length is
1500 feet of ABAM cable (approximately 6 dB of attenuation). Regardless of received signal level,
the peak detectors are held above a minimum level of 0.150 V (typical) to provide immunity from
impulsive noise.
After processing through the data slicers, the received signal goes to the data and timing recovery
section. The data and timing recovery circuits provide an input jitter tolerance better than required
by Pub 62411 and ITU G.823, as shown in Test Specifications,
Depending on the options selected, recovered clock and data signals may be routed through the
jitter attenuator, through the B8ZS/HDB3/AMI decoder, and may be output to the framer as either
bipolar or unipolar data.
Figure
33.
Datasheet