LAN9303-ABZJ Standard Microsystems (SMSC), LAN9303-ABZJ Datasheet - Page 54

• Manufacturer Part Number: LAN9303-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303-ABZJ

• Number Of Primary Switch Ports: 3
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Revision 1.4 (07-07-10)
4.3
4.3.1
PHYADDR_LED5P
E2PSIZE_LED2P
AMDIX2_LED1P
AMDIX1_LED0P
MNGT1_LED4P
MNGT0_LED3P
The Port 1 and Port 2 PHYs support several power management and wakeup features.
Port 1 & 2 PHY Power Management
The Port 1 & 2 PHYs provide independent general power-down and energy-detect power-down modes
which reduce PHY power consumption. General power-down mode provides power savings by
powering down the entire PHY, except the PHY management control interface. General power-down
mode must be manually enabled and disabled as described in
Down," on page
In energy-detect power-down mode, the PHY will resume from power-down when energy is seen on
the cable (typically from link pulses). If the ENERGYON interrupt (INT7) of either PHYs
Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
generate an interrupt. These interrupts are reflected in the
PHY Interrupt Event (PHY_INT2)
the Port 1 PHY. These interrupts can be used to trigger the IRQ interrupt output pin, as described in
Section 5.2.2, "Ethernet PHY Interrupts," on page
Power-Down," on page 101
power-down mode.
Power Management
PIN
101.
Table 4.4 PIN/Shared Strap Mapping
mngt_mode_strap[1]
mngt_mode_strap[0]
phy_addr_sel_strap
eeprom_size_strap
auto_mdix_strap_2
auto_mdix_strap_1
for details on the operation and configuration of the PHY energy-detect
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
STRAP NAME 1
for the Port 2 PHY, and
DATASHEET
54
57. Refer to
is unmasked, then the corresponding PHY will
Port 1 PHY Interrupt Event (PHY_INT1)
Interrupt Status Register (INT_STS) Port 2
Section 7.2.9.1, "PHY General Power-
Section 7.2.9.2, "PHY Energy Detect
STRAP NAME 2
led_pol_strap[5]
led_pol_strap[2]
led_pol_strap[1]
led_pol_strap[0]
led_pol_strap[4]
led_pol_strap[3]
SMSC LAN9303/LAN9303i
Port x PHY
Datasheet
for