LAN9303-ABZJ Standard Microsystems (SMSC), LAN9303-ABZJ Datasheet - Page 30

• Manufacturer Part Number: LAN9303-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303-ABZJ

• Number Of Primary Switch Ports: 3
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Revision 1.4 (07-07-10)
PINS
NUM
1
1
Reference
Port 0 MII
Port 0 MII
Collision
NAME
Output
Clock
P0_OUTCLK
SYMBOL
P0_COL
Table 3.4 Port 0 MII/RMII Pins (continued)
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
DATASHEET
BUFFER
O12/O16
IS/O12/
TYPE
(PD)
(PD)
(PU)
O16
O8
IS
IS
-
30
MII MAC Mode: This pin is an input and is used as
the reference clock for the P0_OUTD[3:0] and
P0_OUTDV pins. It is connected to the transmit
clock of the external PHY.
MII PHY Mode: This pin is an output and is used
as the reference clock for the P0_OUT[3:0] and
P0_OUTDV pins. It is connected to the receive
clock of the external MAC. The output driver is
disabled when the
the
(VPHY_BASIC_CTRL). When operating at
200MBps, the choice of drive strength is based on
the setting of the
in the
(VPHY_SPECIAL_CONTROL_STATUS). A low
selects a 12 mA drive, while a high selects a 16 mA
drive. A series terminating resistor is recommended
for the best PCB signal integrity.
RMII PHY Mode: This pin is an input or an output
running at 50 MHz and is used as the reference
clock for the P0_IND[1:0], P0_INDV,
P0_OUTD[1:0], and P0_OUTDV pins. The choice
of input verses output is based on the setting of the
RMII Clock Direction
Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS). A low
selects P0_OUTCLK as an input and a high selects
P0_OUTCLK as an output.
As an input, the pull-down is normally enabled. The
input buffer and pull-down are disabled when the
Isolate (VPHY_ISO)
Basic Control Register
As an output, the input buffer and pull-down are
disabled. The choice of drive strength is based on
the MII Virtual PHY
bit. A low selects a 12 mA drive, while a high
selects a 16 mA drive. The output driver is disabled
when the
Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL). A series terminating
resistor is recommended for the best PCB signal
integrity.
MII MAC Mode: This pin is an input from the
external PHY and indicates a collision event.
MII PHY Mode: This pin is an output to the external
MAC indicating a collision event. The output driver
is disabled when the
in the
(VPHY_BASIC_CTRL).
RMII PHY Mode: This pin is not used.
Virtual PHY Basic Control Register
Virtual PHY Special Control/Status Register
Virtual PHY Basic Control Register
Isolate (VPHY_ISO)
RMII/Turbo MII Clock Strength
DESCRIPTION
Isolate (VPHY_ISO)
RMII/Turbo MII Clock Strength
bit is set in the
Isolate (VPHY_ISO)
bit in the
(VPHY_BASIC_CTRL).
SMSC LAN9303/LAN9303i
Virtual PHY Special
bit is set in the
Virtual PHY
bit is set in
bit is set
Datasheet
bit