LAN9303-ABZJ Standard Microsystems (SMSC), LAN9303-ABZJ Datasheet - Page 27

• Manufacturer Part Number: LAN9303-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303-ABZJ

• Number Of Primary Switch Ports: 3
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
PINS
NUM
1
1
1
Port 0 MII Input
Port 0 MII Input
Output Data 3
Port 0 Duplex
Configuration
Reference
Port 0 MII
Polarity
NAME
Clock
Strap
Error
DUPLEX_POL_0
P0_OUTD3
P0_INCLK
SYMBOL
P0_INER
Table 3.4 Port 0 MII/RMII Pins (continued)
DATASHEET
BUFFER
O12/O16
Note 3.5
TYPE
(PD)
(PD)
(PD)
(PU)
O8
O8
IS
IS
IS
IS
-
-
-
27
MII MAC Mode: This pin is the RX_ER signal from
the external PHY and indicates a receive error in
the packet.
MII PHY Mode: This pin is the TX_ER signal from
the external MAC and indicates that the current
packet should be aborted. The pull-down and input
buffer are disabled when the
bit is set in the
(VPHY_BASIC_CTRL).
RMII PHY Mode: This pin is not used.
MII MAC Mode: This pin is an input and is used as
the reference clock for the P0_IND[3:0], P0_INER,
and P0_INDV pins. It is connected to the receive
clock of the external PHY.
MII PHY Mode: This pin is an output and is used
as the reference clock for the P0_IND[3:0],
P0_INER, and P0_INDV pins. It is connected to the
transmit clock of the external MAC. The output
driver is disabled when the
is set in the
(VPHY_BASIC_CTRL). When operating at
200MBps, the choice of drive strength is based on
the setting of the
in the
(VPHY_SPECIAL_CONTROL_STATUS). A low
selects a 12 mA drive, while a high selects a 16 mA
drive. A series terminating resistor is recommended
for the best PCB signal integrity.
RMII PHY Mode: This pin is not used.
MII MAC Mode: This pin is the transmit data 3 bit
from the switch to the external PHY.
MII PHY Mode: This pin is the receive data 3 bit
from the switch to the external MAC. The output
driver is disabled when the
is set in the
(VPHY_BASIC_CTRL).
RMII PHY Mode: This pin is not used
This strap selects the default of the duplex polarity
strap for Port 0 MII (duplex_pol_strap_0). See
Note
If the strap is value is 0, a 0 on P0_DUPLEX
means full duplex while a 1 means half duplex. If
the strap value is 1, a 1 on P0_DUPLEX means full
duplex, while a 0 means half duplex.
3.4.
Virtual PHY Special Control/Status Register
Virtual PHY Basic Control Register
Virtual PHY Basic Control Register
Virtual PHY Basic Control Register
RMII/Turbo MII Clock Strength
DESCRIPTION
Isolate (VPHY_ISO)
Isolate (VPHY_ISO)
Isolate (VPHY_ISO)
Revision 1.4 (07-07-10)
bit
bit
bit