LAN9303-ABZJ Standard Microsystems (SMSC), LAN9303-ABZJ Datasheet - Page 48
![no-image](/images/manufacturer_photos/0/6/632/standard_microsystems__smsc__sml.jpg)
LAN9303-ABZJ
Manufacturer Part Number
LAN9303-ABZJ
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9303-ABZJ.pdf
(367 pages)
Specifications of LAN9303-ABZJ
Number Of Primary Switch Ports
3
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9303-ABZJ
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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Revision 1.4 (07-07-10)
STRAP NAME
speed_strap_1
duplex_strap_1
BP_EN_strap_1
FD_FC_strap_1
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
DESCRIPTION
Port 1 Speed Select Strap:
This strap may affect the default value of the following
register bits (x=1):
Refer to the respective register definition sections for
additional information.
Port 1 Duplex Select Strap: This strap affects the default
value of the following register bits (x=1):
Refer to the respective register definition sections for
additional information.
Port 1 Backpressure Enable Strap: Configures the
default value for the
(BP_EN_1)
(MANUAL_FC_1).
Port 1 Full-Duplex Flow Control Enable Strap: This strap
is used to configure the default value of the following
register bits (x=1):
This strap may affect the default value of the following
register bits (x=1):
Refer to the respective register definition sections for
additional information.
Speed Select LSB (PHY_SPEED_SEL_LSB)
Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x)
PHY Mode (MODE[2:0])
Modes Register (PHY_SPECIAL_MODES_x)
10BASE-T Full Duplex
the
(PHY_AN_ADV_x)
Duplex Mode (PHY_DUPLEX)
Control Register (PHY_BASIC_CONTROL_x)
PHY Mode (MODE[2:0])
Modes Register (PHY_SPECIAL_MODES_x)
10BASE-T Full Duplex
Negotiation Advertisement Register (PHY_AN_ADV_x)
Port 1 Full-Duplex Transmit Flow Control Enable
(TX_FC_1)
Enable (RX_FC_1)
Register (MANUAL_FC_1)
Asymmetric Pause
Advertisement Register (PHY_AN_ADV_x)
Port x PHY Auto-Negotiation Advertisement Register
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
bit of the
and
DATASHEET
Port 1 Full-Duplex Receive Flow Control
Port 1 Backpressure Enable
bit of the
bits of the
Port 1 Manual Flow Control Register
48
and
bit of the
bits of the
bits of the
10BASE-T Half Duplex
Port x PHY Auto-Negotiation
Port 1 Manual Flow Control
bit of the
Port x PHY Auto-
Port x PHY Special
Port x PHY Special
Port x PHY Basic
bit of the
bits of
SMSC LAN9303/LAN9303i
PIN / DEFAULT
VALUE
1b
1b
1b
1b
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