LAN9303-ABZJ Standard Microsystems (SMSC), LAN9303-ABZJ Datasheet - Page 51

• Manufacturer Part Number: LAN9303-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303-ABZJ

• Number Of Primary Switch Ports: 3
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
STRAP NAME
manual_FC_strap_2
speed_strap_0
duplex_pol_strap_0
BP_EN_strap_0
FD_FC_strap_0
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
DESCRIPTION
Port 2 Manual Flow Control Enable Strap: Configures the
default value of the
Select (MANUAL_FC_2)
Control Register
This strap affects the default value of the following register
bits (x=2):
Port 0 (External MII) Speed Select Strap: This strap
affects the default value of the following bits in the
PHY Auto-Negotiation Link Partner Base Page Ability
Register
Refer to
information.
This strap also configures the speed for Port 0 when Virtual
Auto-Negotiation fails. Refer to
Detection," on page 103
Port 0 (External MII) Duplex Polarity Strap: This strap
determines the polarity of the P0_DUPLEX pin in MII MAC
mode and affects the default value of the following bits in
the
Ability Register
Refer to
information.
Port 0 (External MII) Backpressure Enable Strap:
Configures the default value of the
Enable (BP_EN_0)
Register
Port 0 (External MII) Full-Duplex Flow Control Enable
Strap: Configures the default value of the
Flow Control Enable (TX_FC_0)
Control Enable (RX_FC_0)
Control Register
This strap affects the default value of the following register
bits:
Asymmetric Pause
x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x).
100BASE-X Full Duplex
100BASE-X Half Duplex
10BASE-T Full Duplex
10BASE-T Half Duplex
100BASE-X Full Duplex
100BASE-X Half Duplex
10BASE-T Full Duplex
10BASE-T Half Duplex
Asymmetric Pause
Auto-Negotiation Link Partner Base Page Ability Register
(VPHY_AN_LP_BASE_ABILITY)
Virtual PHY Auto-Negotiation Link Partner Base Page
Section 13.2.6.6
Section 13.2.6.6
(VPHY_AN_LP_BASE_ABILITY):
(MANUAL_FC_0).
(VPHY_AN_LP_BASE_ABILITY):
DATASHEET
(MANUAL_FC_2).
(MANUAL_FC_0).
Port 2 Full-Duplex Manual Flow Control
bit of the
and
and
51
for additional information.
bit in the
Symmetric Pause
and
and
Pause
bits in the
Port 0 Manual Flow Control
Table 13.7
Table 13.7
Section 7.3.1.1, "Parallel
bits of the
and
Port 2 Manual Flow
Port 0 Backpressure
Port 0 Receive Flow
Port 0 Manual Flow
for more
for more
Port 0 Transmit
bits of the
Virtual PHY
Virtual
Port
PIN / DEFAULT
VALUE
0b
1b
DUPLEX_POL_0
1b
1b
Revision 1.4 (07-07-10)