XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 87
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
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X-Ref Target - Figure 2-20
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
PSDONE
CLKFB
CLKFX
PSCLK
CLKIN
DO(0)
DO(1)
DO(2)
PSEN
DO(3)
Status Flags
The example in
shift overflow and CLKIN/CLKFB/CLKFX failure.
•
•
•
•
Clock Event 1
Prior to the beginning of this timing diagram, CLK0 (not shown) is already phase-
shifted at its maximum value. At clock event 1, PSDONE is asserted. However, since
the DCM has reached its maximum phase-shift capability no phase adjustment is
performed. Instead, the phase-shift overflow status pin DO(0) is asserted to indicate
this condition.
Clock Event 2
The CLKFX output stops toggling. Within 257 to 260 clock cycles after this event, the
CLKFX stopped status DO(2) is asserted to indicate that the CLKFX output stops
toggling.
Clock Event 3
The CLKFB input stops toggling. Within 257 to 260 clock cycles after this event, the
CLKFB stopped status DO(3) is asserted to indicate that the CLKFB output stops
toggling.
Clock Event 4
The CLKIN input stops toggling. Within 9 clock cycles after this event, DO(1) is
asserted to indicate that the CLKIN output stops toggling.
1
2
Figure 2-20: Status Flags Example
Figure 2-20
www.xilinx.com
shows the behavior of the status flags in the event of a phase-
3
257 - 260 Cycles
4
DCM Timing Models
ug190_2_21_042406
87
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