XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 44
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XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
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Chapter 1: Clock Resources
44
BUFR Attributes and Modes
Clock division in the BUFR is controlled in software through the BUFR_DIVIDE attribute.
Table 1-8
Table 1-8: BUFR_DIVIDE Attribute
The propagation delay through BUFR is different for BUFR_DIVIDE = 1 and
BUFR_DIVIDE = BYPASS. When set to 1, the delay is slightly more than BYPASS. All other
divisors have the same delay BUFR_DIVIDE = 1. The phase relationship between the input
clock and the output clock is the same for all possible divisions except BYPASS.
The timing relationship between the inputs and output of BUFR when using the
BUFR_DIVIDE attribute is illustrated in
attribute is set to three. Sometime before this diagram CLR was asserted.
X-Ref Target - Figure 1-21
In
•
•
•
•
•
Notes:
1. Location constraint is available for BUFR.
BUFR_DIVIDE
Attribute Name
Figure
Before clock event 1, CE is asserted High.
After CE is asserted and time T
three rate of the input I. T
speed specification.
Note: The duty cycle is not 50/50 for odd division. The Low pulse is one cycle of I
longer.
At time event 2, CLR is asserted. After T
toggling.
At time event 3, CLR is deasserted.
At time T
rate of I.
CLR
CE
O
I
lists the possible values when using the BUFR_DIVIDE attribute.
1-21:
Figure 1-21: BUFR Timing Diagrams with BUFR_DIVIDE Values
BRCKO_O
1
Defines whether the output clock is a divided
version of the input clock.
after clock event 4, O begins toggling again at the divided by three
T
www.xilinx.com
BRCKO_O
BRCKO_O
BRCKO_O
Description
and other timing numbers are best found in the
Figure
, the output O begins toggling at the divide by
BRDO_CLRO
T
BRDO_CLRO
1-21. In this example, the BUFR_DIVIDE
from time event 2, O stops
2
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
1, 2, 3, 4, 5, 6, 7, 8
BYPASS (default)
3
Possible Values
4
ug190_1_21_041808
T
BRCKO_O
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