XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 10
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
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10
DCM Attributes
DCM Design Guidelines
DCM Control and Data Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DCM Clock Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DCM Status and Data Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
CLKDV_DIVIDE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
CLKFX_MULTIPLY and CLKFX_DIVIDE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
CLKIN_PERIOD Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
CLKIN_DIVIDE_BY_2 Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
CLKOUT_PHASE_SHIFT Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
CLK_FEEDBACK Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DESKEW_ADJUST Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DFS_FREQUENCY_MODE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DLL_FREQUENCY_MODE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DUTY_CYCLE_CORRECTION Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DCM_PERFORMANCE_MODE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
FACTORY_JF Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PHASE_SHIFT Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
STARTUP_WAIT Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Clock Deskew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Frequency Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Dynamic Reconfiguration Clock Input - DCLK
Reset Input - RST
Phase-Shift Increment/Decrement Input - PSINCDEC
Phase-Shift Enable Input - PSEN
Dynamic Reconfiguration Data Input - DI[15:0]
Dynamic Reconfiguration Address Input - DADDR[6:0]
Dynamic Reconfiguration Write Enable Input - DWE
Dynamic Reconfiguration Enable Input - DEN
1x Output Clock - CLK0
1x Output Clock, 90° Phase Shift - CLK90
1x Output Clock, 180° Phase Shift - CLK180
1x Output Clock, 270° Phase Shift - CLK270
2x Output Clock - CLK2X
2x Output Clock, 180° Phase Shift - CLK2X180
Frequency Divide Output Clock - CLKDV
Frequency-Synthesis Output Clock - CLKFX
Frequency-Synthesis Output Clock, 180° - CLKFX180
Locked Output - LOCKED
Phase-Shift Done Output - PSDONE
Status or Dynamic Reconfiguration Data Output - DO[15:0]
Dynamic Reconfiguration Ready Output - DRDY
Clock Deskew Operation
Input Clock Requirements
Input Clock Changes
Output Clocks
DCM During Configuration and Startup
Deskew Adjust
Characteristics of the Deskew Circuit
Frequency Synthesis Operation
Frequency Synthesizer Characteristics
Phase-Shifting Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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www.xilinx.com
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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