XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 310
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 310 of 385
- Download datasheet (14Mb)
Chapter 6: SelectIO Resources
310
Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank (Continued)
Voltage
2.5V
LVCMOS25_2_slow
LVCMOS25_4_slow
LVCMOS25_6_slow
LVCMOS25_8_slow
LVCMOS25_12_slow
LVCMOS25_16_slow
LVCMOS25_24_slow
LVCMOS25_2_fast
LVCMOS25_4_fast
LVCMOS25_6_fast
LVCMOS25_8_fast
LVCMOS25_12_fast
LVCMOS25_16_fast
LVCMOS25_24_fast
LVDCI_25 50 Ω
SSTL2_I
SSTL2_I_DCI
SSTL2_II
SSTL2_II_DCI
HSLVDCI_25 50 Ω
DIFF_SSTL_I
DIFF_SSTL_I_DCI
DIFF_SSTL_II
DIFF_SSTL_II_DCI
LVPECL_25
BLVDS_25
LVDS_25
LVDSEXT_25
RSDS_25
HT_25
IOSTANDARD
www.xilinx.com
Limit per 20-pin Bank
20
20
20
20
20
20
20
20
20
20
20
20
20
15
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Limit per 40-pin Bank
40
40
40
40
40
40
40
40
40
40
40
40
40
30
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
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