XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 120
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
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Chapter 4: Block RAM
Additional Block RAM Features in Virtex-5 Devices
X-Ref Target - Figure 4-5
120
CLK
WE
Optional Output Registers
Independent Read and Write Port Width Selection
EN
Optional
Inverter
Address
DI
The optional output registers improve design performance by eliminating routing delay to
the CLB flip-flops for pipelined operation. An independent clock and clock enable input is
provided for these output registers. As a result the output data registers hold the value
independent of the input register operation.
Each block RAM port has control over data width and address depth (aspect ratio). The
true dual-port block RAM in Virtex-5 FPGAs extends this flexibility to Read and Write
where each individual port can be configured with different data bit widths. For example,
port A can have a 36-bit Read width and a 9-bit Write width, and port B can have a 18-bit
Read width and a 36-bit Write width. See
If the Read port width differs from the Write port width, and is configured in
WRITE_FIRST mode, then DO shows valid new data for all the enabled write bytes. The
DO port outputs the original data stored in memory for all not enabled bytes.
Independent Read and Write port width selection increases the efficiency of implementing
a content addressable memory (CAM) in block RAM. This option is available for all
Virtex-5 FPGA true dual-port RAM port sizes and modes.
Figure 4-5: Block RAM Logic Diagram (One Port Shown)
Register
Strobe
Write
(common to
both ports)
Memory
Array
www.xilinx.com
Read
Strobe
Control Engine
D
Latches
Block RAM Attributes, page
Figure 4-5
Latch
Enable
Q
Configurable Options
shows the optional output register.
D
Register
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Q
128.
UG190_4_06_040606
DO
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